MAX1072 Datasheet, PDF (8/18 Pages) Maxim Integrated Products – 1.8Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs

1.8Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
PIN
1
2
3
4
5, 11
6
7
8
9
10
12
—
NAME
AIN-
REF
RGND
V_DD
N.C.
GND
V_L
DOUT
CNVST
SCLK
AIN+
EP
Pin Description
Negative Analog Input
FUNCTION
External Reference Voltage Input. V_REF sets the analog input range. Bypass REF with a 0.01µF
capacitor and a 4.7µF capacitor to RGND.
Reference Ground. Connect RGND to GND.
Positive Analog Supply Voltage (+4.75V to +5.25V). Bypass V_DD with a 0.01µF capacitor and a 10µF
capacitor to GND.
No Connection
Ground. GND is internally connected to EP.
Positive Logic Supply Voltage (1.8V to V_DD). Bypass V_L with a 0.01µF capacitor and a 10µF capacitor
to GND.
Serial Data Output. Data is clocked out on the rising edge of SCLK.
Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.
Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
Positive Analog Input
Exposed Paddle. EP is internally connected to GND.
Detailed Description
The MAX1072/MAX1075 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 10-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1072/MAX1075.
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1072/MAX1075, which is composed of
a T/H, a comparator, and a switched-capacitor digital-to-
analog converter (DAC). The T/H enters its tracking mode
on the 14th SCLK rising edge of the previous conversion.
Upon power-up, the T/H enters its tracking mode immedi-
ately. The positive input capacitor is connected to AIN+.
The negative input capacitor is connected to AIN-. The
T/H enters its hold mode on the falling edge of CNVST
and the difference between the sampled positive and
negative input voltages is converted. The time required
for the T/H to acquire an input signal is determined by
how quickly its input capacitance is charged. If the input
signal’s source impedance is high, the acquisition time
lengthens. The acquisition time, t_ACQ, is the minimum
time needed for the signal to be acquired. It is calculated
by the following equation:
t_ACQ ≥ 8 × (RS + R_IN) × 16pF
where R_IN = 200Ω, and RS is the source impedance of
the input signal.
Note: t_ACQ is never less than 104ns and any source
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
Input Bandwidth
The ADC’s input-tracking circuitry has a 20MHz small-
signal bandwidth, making it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input
to V_DD and GND allow the analog input pins to swing
from GND - 0.3V to V_DD + 0.3V without damage. Both
inputs must not exceed V_DD or be lower than GND for
accurate conversions.
8 _______________________________________________________________________________________