MAX157 Datasheet, PDF (8/16 Pages) Maxim Integrated Products – Dual-Channel CardBus and PCMCIA VCC/VPP Power-Switching Networks

+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
The capacitive digital-to-analog converter (DAC)
adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 10-bit
resolution. This action is equivalent to transferring a
16pF · [(V_IN+) - (V_IN-)] charge from C_HOLD to the bina-
ry-weighted capacitive DAC, which in turn forms a digi-
tal representation of the analog input signal.
Track/Hold
The ADC’s T/H stage enters its tracking mode on the
falling edge of CS/SHDN. For the MAX157 (single-
ended inputs), IN- is connected to GND and the con-
verter samples the positive (“+”) input. For the MAX159
(pseudo-differential inputs), IN- connects to the nega-
tive input (“-”), and the difference of [(V_IN+) - (V_IN-)] is
sampled. At the end of the conversion, the positive
input connects back to IN+ and C_HOLD charges to the
input signal.
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
t_ACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
t_ACQ = 7(R_S + R_IN)C_IN
where R_S is the source impedance of the input signal,
R_IN (9kΩ) is the input resistance, and C_IN (16pF) is the
input capacitance of the ADC. Source impedances
below 4kΩ have no significant impact on the AC perfor-
mance of the MAX157/MAX159.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor forms
an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX157/MAX159 T/H stage offers both a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
makes it possible to use the parts for digitizing high-
speed transients and measuring periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
required, it is usually best to choose a continuous
or switched-capacitor filter, such as the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband re-
sponse.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V_DD and GND, allow each input channel to
swing within GND - 300mV to V_DD + 300mV without
damage. However, for accurate conversions both
inputs must not exceed V_DD + 50mV or be less than
GND - 50mV.
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.
CS/SHDN
SCLK
CONTROL
LOGIC
INTERNAL
CLOCK
CH0
(CH+)
CH1
(CH-)
ANALOG
INPUT
MUX
(2 CHANNEL)
SCLK
10+2 BIT
T/H IN SAR OUT
ADC
REF
( ) ARE FOR MAX159
OUTPUT ^DOUT
REGISTER
MAX157
MAX159
Figure 2. MAX157/MAX159 Simplified Functional Diagram
CH1
(CH-)
CH0
(CH+)
CAPACITIVE DAC
REF
INPUT
MUX _–
+
ZERO
COMPARATOR
C_SWITCH
C_HOLD
16pF
R_IN
9k
TRACK
HOLD
TO SAR
T/H
CONTROL
GND
LOGIC
SINGLE-ENDED MODE: CHO, CH1 = IN+; GND = IN-
DIFFERENTIAL MODE: CH+ = IN+; CH- = IN-
( ) ARE FOR MAX159
Figure 3. Analog Input Channel Structure
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