MAX157 Datasheet, PDF (4/16 Pages) Maxim Integrated Products – Dual-Channel CardBus and PCMCIA VCC/VPP Power-Switching Networks

+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = +2.7V to +5.25V, V_REF = 2.5V, 0.1µF capacitor at REF, f_SCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Positive Supply Voltage
Positive Supply Current
Positive Supply Current
V_DD
I_DD
Operating mode
I_DD
Shutdown, CS/SHDN = GND
+2.7
+5.25
V
0.9
2.0
mA
0.2
5
µA
Power-Supply Rejection
(Note 9)
PSR V_DD = 2.7V to 5.25V, full-scale input
±0.15
mV
TIMING CHARACTERISTICS (Figure 7)
(V_DD = +2.7V to +5.25V, V_REF = 2.5V, 0.1µF capacitor at REF, f_SCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Wake-Up Time
CS/SHDN Fall to Output Enable
t_WAKE
t_DV
C_L = 100pF (Figure 1)
2.5
µs
120
ns
CS/SHDN Rise to Output
Disable
t_TR
C_L = 100pF (Figure 1)
120
ns
SCLK Fall to Output Data Valid
t_DO
C_L = 100pF
20
SCLK Clock Frequency
External clock
0.1
f_{SCLK Internal clock, SCLK for data transfer only}
0
External clock
215
SCLK Pulse Width High
t_CH
Internal clock, SCLK for data transfer only
(Note 8)
50
120
ns
2.17
MHz
5
ns
External clock
215
SCLK Pulse Width Low
t_CL
Internal clock, SCLK for data transfer only
(Note 8)
50
ns
SCLK to CS/SHDN Setup
CS/SHDN Pulse Width
t_SCLKS
t_CS
60
ns
60
ns
Note 1: Tested at V_DD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: The on channel is grounded; the sine wave is applied to off channel (MAX157 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to V_DD (MAX159 only).
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as V_FS(2.7V) - V_FS(5.25V).
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