MAX157 Datasheet, PDF (13/16 Pages) Maxim Integrated Products – Dual-Channel CardBus and PCMCIA VCC/VPP Power-Switching Networks

+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
SCLK
CS/SHDN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DOUT
CHID D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
SAMPLING INSTANT MSB
LSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z
HIGH-Z
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
V_DD
V_DD
SCLK
SCK
DOUT
SDI
CS/SHDN
I/O
MAX157
MAX159
PIC16/PIC17
GND
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
star-point (Figure 11) connecting the two ground sys-
tems (analog and digital). For lowest-noise operation,
ensure the ground return to the star ground’s power
supply is low impedance and as short as possible.
Route digital signals far away from sensitive analog and
reference inputs.
High-frequency noise in the power supply (V_DD) could
influence the proper operation of the ADC’s fast com-
parator. Bypass V_DD to the star ground with a network
of two parallel capacitors, 0.1µF and 1µF, located as
close as possible to the power supply pin of the
MAX157/MAX159. Minimize capacitor lead length for
best supply-noise rejection and add an attenuation
resistor (10Ω) if the power supply is extremely noisy.
SCLK
CS/SHDN
1ST BYTE READ
1 2345678
2ND BYTE READ
9 10 11 12 13 14 15 16
DOUT*
CHID D9 D8 D7 D6
SAMPLING INSTANT _MSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z
HIGH-Z
D5
D4 D3 D2 D1 D0 S1 S0
LSB
Figure 10b. SPI Interface Timing Sequence with PIC16/17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
+3V
R* = 10Ω
1µF
POWER SUPPLIES
+3V GND
0.1µF
V_DD
GND
MAX157
MAX159
* OPTIONAL FILTER RESISTOR
Figure 11. Power-Supply Bypassing and Grounding
+3V DGND
DIGITAL
CIRCUITRY
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