MAX1492 Datasheet, PDF (8/35 Pages) Maxim Integrated Products – 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers

3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
PIN
MAX1492 MAX1494
1
30
2
31
3
32
4
1
5
2
6
3
7
4
8
5
9
6
10
7
11
8
12
9
13
10
14
11
15
12
16
13
17
14
18
15
19
16
20
17
21
18
22
19
23
20
Pin Description
NAME
FUNCTION
External Clock Input. When the EXTCLK bit in the control register is set, CLK is the
CLK
master clock input for the modulator and the filter (frequency = 4.9152MHz). When the
EXTCLK bit in the control register is reset, the internal clock is used. Connect CLK to
GND or DV_DD when the internal oscillator is used.
DV_DD
GND
AV_DD
Digital Power Input. Connect DV_DD to a 2.7V to 5.25V power supply. Bypass DV_DD to
GND with 0.1µF and 4.7µF capacitors.
Ground
Analog Power Input. Connect AV_DD to a 2.7V to 5.25V power supply. Bypass AV_DD to
GND with 0.1µF and 4.7µF capacitors.
AIN+
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to
GND with a 0.1µF or greater capacitor.
AIN-
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to
GND with a 0.1µF or greater capacitor.
REF-
Negative Reference Input. During internal reference operation, connect REF- to GND.
For external reference operation, bypass REF- to GND with a 0.1µF capacitor and set
V_REF- from -2.2V to +2.2V, provided V_REF+ > V_REF-.
REF+
Positive Reference Input. During internal reference operation, connect a 4.7µF capacitor
from REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1µF
capacitor and set V_REF+ from -2.2V to +2.2V, provided V_REF+ > V_REF-.
LOWBATT ^{Low-Battery Input. When VLOWBATT < 2.048V (typ), the LOWBATT symbol on LCD turns}
on and the LOWBATT bit latches high in the status register.
EOC
CS
Active-Low, End-of-Conversion Logic Output. A logic-low at EOC indicates that a new
ADC result is available in the ADC result register.
Active-Low Chip-Select Input. Forcing CS low activates the serial interface.
DIN
Serial Data Input. Data present at DIN is shifted into the internal registers in response to
a rising edge at SCLK when CS is low.
SCLK
Serial Clock Input. Apply an external clock to SCLK to facilitate communication through
the serial bus. SCLK can idle high or low.
DOUT
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
Serial Data Output. DOUT presents serial data in response to register queries. Data
shifts out on the falling edge of SCLK. DOUT goes high impedance when CS is high.
LCD Segment 1 Driver
LCD Segment 2 Driver
LCD Segment 3 Driver
LCD Segment 4 Driver
LCD Segment 5 Driver
LCD Segment 6 Driver
LCD Segment 7 Driver
LCD Segment 8 Driver
LCD Segment 9 Driver
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