MAX1492 Datasheet, PDF (5/35 Pages) Maxim Integrated Products – 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers

3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
TIMING CHARACTERISTICS (Notes 10, 11 and Figure 13)
(AV_DD = DV_DD = 2.7V to +5.25V, GND = 0, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Operating Frequency
f_SCLK
0
4.2
MHz
SCLK Pulse-Width High
t_CH
100
ns
SCLK Pulse-Width Low
t_CL
100
ns
DIN to SCLK Setup
t_DS
50
ns
DIN to SCLK Hold
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
t_DH
t_CSS
t_CSH
0
ns
50
ns
0
ns
SCLK Fall to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
t_DO
C_LOAD = 50pF (Figures 18, 19)
t_TR
C_LOAD = 50pF (Figures 18, 19)
t_DV
C_LOAD = 50pF (Figures 18, 19)
120
ns
120
ns
120
ns
Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error
and offset error.
Note 2: Offset calibrated. See the OFFSET_CAL1 and OFFSET_CAL2 sections in the On-Chip Registers section.
Note 3: Offset nulled.
Note 4: Drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6: V_AIN+ or V_AIN- = -2.2V to +2.2V. V_REF+ or V_REF- = -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only.
Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
Note 8: CLK and SCLK are idle.
Note 9: Power-supply currents are measured with all digital inputs at either GND or DV_DD and with the device in internal clock mode.
Note 10: All input signals are specified with t_RISE = t_FALL = 5ns (10% to 90% of DV_DD) and are timed from a voltage level of 50% of
DV_DD, unless otherwise noted.
Note 11: See the serial-interface timing diagrams.
_______________________________________________________________________________________ 5