MAX1492 Datasheet, PDF (22/35 Pages) Maxim Integrated Products – 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers

3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
Command Byte (Write Only):
MSB
Bit 7
START (1)
Bit 6
R/W
Bit 5
RS4
Bit 4
RS3
START:
(R/W):
Start Bit. The first 1 clocked into the
MAX1492/MAX1494 is the first bit of the
command byte.
Read/Write. Set this bit to 1 to read from
the specified register. Set this bit to 0 to
write to the selected register. Note that
Status Register (Read Only):
MSB
SIGN
OVER
UNDER LOW_BATT
Default values: 00h
This register contains the status of the conversion
results.
SIGN:
Latched Negative-Polarity Indicator.
Latches high when the result is negative.
Clears by reading the status register,
unless the condition remains true.
OVER:
Overrange Bit. Latches high if an over-
range condition occurs (the ADC result is
larger than the value in the overrange reg-
ister). Clears by reading the status regis-
ter, unless the condition remains true.
Control Register (Read/Write):
MSB
Bit 15
SPI/ADC
Bit 14
EXTCLK
Bit 13
INTREF
Bit 12
DP_EN
Bit 7
HOLD
Bit 6
PEAK
Bit 5
RANGE
Bit 4
CLR
Default values: 0000h
This register is the primary control register for the
MAX1492/MAX1494. It is a 16-bit read/write register. It
is used to indicate the desired clock and reference
LSB
Bit 3
Bit 2
Bit 1
Bit 0
RS2
RS1
RS0
X
certain registers are read-only. Write com-
mands to a read-only register are
ignored.
(RS4–RS0): Register Address Bits. RS4 to RS0 specify
which register is accessed.
X:
Don’t care.
LSB
DRDY
0
0
0
UNDER:
Underrange Bit. Latches high if an under-
range condition occurs (the ADC result is
less than the value in the underrange regis-
ter). Clears by reading the status register,
unless the condition remains true.
LOW_BATT: Low-Battery Bit. Latches high if the voltage
at the LOWBATT is lower than 2.048V (typ).
Clears by reading the status register,
unless the condition remains true.
DRDY:
Data-Ready Bit. Latches high to indicate
a completed conversion result with valid
data. Read the ADC Result-Register 1 to
clear this bit.
Bit 11
DPSET2
Bit 3
SEG_SEL
Bit 10
DPSET1
Bit 9
PD_DIG
Bit 2
Bit 1
OFFSET_CAL1 OFFSET_CAL2
Bit 8
PD_ANA
LSB
Bit 0
0
source. It sets the LCD controls, range modes, power-
down modes, offset calibration, and the reset register
function (CLR).
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