MAX14912 Datasheet, PDF (8/30 Pages) Maxim Integrated Products – Low Power and Heat Dissipation

MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
AC Electrical Characteristics (continued)
(V_DD = +10V to +36V, V₅ = +4.5V to +5.5V, V_L = +1.6V to +5.5V, T_A = -40°C to +125°C, unless otherwise noted. Typical values are at
T_A = +25°C and V_DD = +24V, CDCDC = 10µF, LDCDC = 100µH, CFLY = 200nF, CPUMP = 10µF, unless otherwise noted.
PARAMETER
SYMBOL
CRC ERROR DETECTION (CERR/IN4)
CONDITIONS
MIN
TYP
MAX UNITS
SRIAL = high, CRC/IN3 = high,
t_{PDL_CERR}
OUT_ detects a CRC error on SDI
14.5
ns
Propagation Delay
data, I_SOURCE = 5mA
SRIAL = high, CRC/IN3 = high,
t_{PDH_CERR}
OUT_ clears/CERR/IN4,
I_SOURCE = 5mA
17
ns
WATCHDOG TIMER
Watchdog Timeout Accuracy t_{WD_ACC}
SRIAL = high, WDEN/IN5 = high.
See Table 5 for watchdog timeout
-10
selection.
+10
%
GLITCH FILTERS
Pulse Length of Rejected
Glitch
t_{FPL_GF}
FLTR = high, on EN, CS, _IN_ pins
FLTR = X, SRIAL and PUSHPL pins
80
ns
170
FLTR = high, on EN, CS, _IN_ pins
260
Passes Pulse Length
t_{FD_GF}
FLTR = X, SRIAL and PUSHPL pins 550
ns
FLTR = high, on EN, CS, _IN_ pins
140
Glitch Filter Delay Time
t_{D_GF}
FLTR = X, SRIAL and PUSHPL pins
320
ns
SPI TIMING CHARACTERISTICS
2.5V ≤ V_L < 5.5V
CLK Clock Period
CLK Pulse-Width High
CLK Pulse-Width Low
t_CH+CL
t_CH
t_CL
CS Fall-to-CLK Rise Time
t_CSS
SDI Hold Time
SDI Setup Time
Output Data Propagation
Delay
SDO Rise-and-Fall Times
CS Hold Time
t_DH
t_DS
t_DO
t_FT
t_CSH
CS Pulse Width High
t_CSPW
FLTR = low (Note 5)
FLTR = high
C_L = 10pF. CLK falling-edge to
SDO stable
FLTR = low (Note 5).
FLTR = high
50
ns
10
ns
10
ns
12
ns
260
5
ns
5
ns
30
ns
1
ns
40
ns
15
ns
260
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