MAX14912 Datasheet, PDF (27/30 Pages) Maxim Integrated Products – Low Power and Heat Dissipation

MAX14912/MAX14913
Octal High-Speed, High-Side
Switch/Push-Pull Driver
Error Detection on the Serial Interface
CRC Detection
In serial mode (SRIAL = high), error-detection of the serial
data can be enabled to minimize incorrect operation/
misinformation due to data corruption of the SDI/SDO sig-
nals. If enabled, the devices performs error detection on
SDI data received from the controller, calculates a CRC
on the SDO data sent to the controller, and appends a
check byte to the SDO diagnostics/status data it sends to
the controller. This ensures that the data it receives from
the controller (setting/configuration), as well as the data
that it sends to the controller (diagnostics/status), has a
low likelihood of undetected errors.
Setting the CRC/IN3 input high enables CRC error detection.
A CRC frame-check sequence (FCS) is then sent along
with each serial transaction. The 7-bit FCS is based on the
generator polynomial (x7 + x5 + x4 + x2 + x + 1). The CRC
initialization condition is 0x7F. When CRC is enabled, the
device expects a check byte appended to the 8 or 16-bit
SDI program/configuration data it receives. The check
byte has the format shown in Figure 10.
The 7-bit FCS bits (CRI_) are calculated on the 8/16-bit
data, including the 1 in the first position of the check byte.
Therefore, the CRC is calculated on 9 or 17 bits. CRI1 is
the LSB of the FCS.
The device verifies the received FCS. If no error is
detected, it sets the OUT_ outputs and/or changes con-
figuration per the SDI data. If a CRC error is detected, the
device does not change the OUT_ outputs and/or does
not change its configuration. Instead, it sets the CERRB/
IN4 output low (i.e., the open-drain CERRB/IN4 nMOS
output transistor is turned on) and sets the CERR (CRC
error) bit in the check byte that it appends to the 8/16-bit
SDO diagnostic/status data returned to the controller dur-
ing the following serial communication cycle. In command
SPI mode, register 6 also reflects an CRC error condition.
The check byte the device appends to the 8/16-bit diag-
nostics/status data has the format shown in Figure 11.
CERR is the error-feedback bit that it sends back to the
controller to signal that a CRC error was detected on the
previous SDI data reception. Note that CERR is one state
delayed (i.e., it indicates if an error was detected in the
previous SPI data reception). The reason for the one-
cycle delay is due to the daisy-chain scheme.
CRO_ are the CRC bits that the device calculates on
the 8/16-bit diagnostics and/or status data, including the
CERR bit (i.e., calculated on 9/17 bits). This allows the
controller to check for errors on the SDO data received
from the device.
Clock Count for Multiples of 8
For each SPI cycle (between CS going low to CS going
high), the device counts the number of CLK pulses. The
8CKmult error flag (see Table 7) is asserted (goes high)
and the FAULT pin is asserted (goes low) if the counted
CLK pulses are not a multiple of 8. In this case, the SDi
data is ignored.
C
C
C C CC C C C
Figure 10. SDI Check Byte Expected from Controller
CS
C
S
C C CC C C C
Figure 11. SDO Check Byte Sent by Device
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