MAX148 Datasheet, PDF (8/24 Pages) Maxim Integrated Products – +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
_______________Detailed Description
The MAX148/MAX149 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX148/
MAX149.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from the fol-
lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at IN+
is sampled. The return side (IN-) must remain stable within
±0.5LSB (±0.1LSB for best results) with respect to AGND
during a conversion. To accomplish this, connect a 0.1µF
capacitor from IN- (the selected analog input) to AGND.
During the acquisition interval, the channel selected
as the positive input (IN+) charges capacitor C_HOLD.
The acquisition interval spans three SCLK cycles and
ends on the falling SCLK edge after the last bit of the
input control word has been entered. At the end of the
acquisition interval, the T/H switch opens, retaining
charge on C_HOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching C_HOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0V
within the limits of 10-bit resolution. This action is equiv-
alent to transferring a 16pF x [(V_IN+) - (V_IN-)] charge
from C_HOLD to the binary-weighted capacitive DAC,
which in turn forms a digital representation of the analog
input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-| is sampled. At the end of the
conversion, the positive input connects back to IN+,
and C_HOLD charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
CS ¹⁸
SCLK ¹⁹
DIN ¹⁷
SHDN ¹⁰
CH0 ¹
CH1 ²
CH2 ³
CH3 ⁴
CH4 ⁵
CH5 ⁶
CH6 ⁷
CH7 ⁸
COM ⁹
REFADJ ¹²
VREF ¹¹
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
ANALOG
INPUT
MUX
OUTPUT
SHIFT
REGISTER
T/H
CLOCK
IN _10+2-BIT
SAR
ADC _OUT
REF
+1.21V
REFERENCE
(MAX149)
A ≈ 2.06*
20k
+2.500V
MAX148
MAX149
15 _DOUT
16 _SSTRB
20 _VDD
14 _DGND
13 _AGND
*A ≈ 2.00 (MAX148)
Figure 3. Block Diagram
CAPACITIVE DAC
VREF
CH0
INPUT
MUX
C_HOLD
–+
COMPARATOR
ZERO
CH1
16pF
CH2
R_IN
CH3
C_SWITCH
9k
CH4
HOLD
TRACK
CH5
AT THE SAMPLING INSTANT,
CH6
CH7
T/H
SWITCH
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
COM
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
Figure 4. Equivalent Input Circuit
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