MAX148 Datasheet, PDF (12/24 Pages) Maxim Integrated Products – +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
CS
SCLK
DIN
DOUT
t_CSS
t_CSH
t_DS
t_DH
t_DV
•••
t_CH
t_CL
•••
•••
•••
Figure 7. Detailed Serial-Interface Timing
t_CSH
t_DO
t_TR
CS
SSTRB
•••
t_SDV
•••
•••
t_STR
•••
t_SSTRB
t_SSTRB
SCLK
••••
• • ••
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
MAX148/MAX149. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). SSTRB and DOUT go into a high-impedance
state when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 8 shows the SSTRB
timing in external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
Internal Clock
In internal clock mode, the MAX148/MAX149 generate
their own conversion clocks internally. This frees the µP
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