MAX148 Datasheet, PDF (15/24 Pages) Maxim Integrated Products – +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
CS
SCLK
DIN
DOUT
SSTRB
1
8
15 1
8
15 1
S
CONTROL BYTE 0
S
CONTROL BYTE 1
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
S CONTROL BYTE 2
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS
1
8
SCLK
16
1
8
DIN
S CONTROL BYTE 0
S CONTROL BYTE 1
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 0
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
•••
16
•••
•••
B9 B8 B7 B6 • • •
CONVERSION RESULT 1
CLOCK
MODE
SHDN
DIN
SETS EXTERNAL
CLOCK MODE
SXXXXX11
DOUT
10 + 2 DATA BITS
MODE
POWERED UP
EXTERNAL
EXTERNAL
SETS SOFTWARE
POWER-DOWN
SX X XXX0 0
SETS EXTERNAL
CLOCK MODE
S XX XXX1 1
10 + 2 DATA BITS
VALID
DATA
POWERED UP
SOFTWARE
POWER-DOWN
INVALID
DATA
HARDWARE
POWER-
DOWN
POWERED UP
Figure 12a. Timing Diagram Power-Down Modes, External Clock
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7µF compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
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