MAX1458 Datasheet, PDF (8/20 Pages) Maxim Integrated Products – 1%-Accurate, Digitally Trimmed Sensor Signal Conditioner

1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Table 4. EEPROM Memory Map
EE Address
Contents
0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00
1000
Configuration
EE Address
Contents
1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10
1 0 0 1 MSB
Offset
LSB
EE Address
Contents
2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20
1 0 1 0 MSB
Offset TC
LSB
EE Address
Contents
3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30
1 0 1 1 MSB
FSO
LSB
EE Address
Contents
4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40
1 1 0 0 MSB
FSOTC
LSB
Reserved*
5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50
0000000000000000
EE Address
Contents
6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60
0000
User defined bits
EE Address
Contents
7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70
0000
User defined bits
= Reserved Bits
Note: The MAX1458 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration
and DAC registers will not be updated correctly.
* The contents of the Reserved EE Address 50–5F must all be reset to zero.
• Configuration register (Table 3)
• 12-bit calibration coefficients for the Offset and FSO
DACs
• 12-bit compensation coefficients for the Offset TC
and FSOTC DACs
• Two general-purpose registers available to the user
for storing process information such as serial num-
ber, batch date, and check sums
Program the EEPROM one bit at a time. The bits have
addresses from 0 to 127 (7F hex).
Configuration Register
The configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi-
cients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (R_FTC and
R_ISRC).
DAC Registers
The Offset, Offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
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