MAX1458 Datasheet, PDF (6/20 Pages) Maxim Integrated Products – 1%-Accurate, Digitally Trimmed Sensor Signal Conditioner

1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Table 1. Input-Referred Offset DAC
Correction Values
VALUE
+7
+6
+5
+4
+3
+2
+1
+0
-0
-1
-2
-3
-4
-5
-6
-7
IRO DAC
OFFSET OFFSET
CORREC- CORREC-
TION
TION AT
% of V_DD V_DD = 5V
SIGN C2 C1 C0
(%)
(mV)
1
111
+1.25
+63
1
110
+1.08
+54
1
101
+0.90
+45
1
100
+0.72
+36
1
011
+0.54
+27
1
010
+0.36
+18
1
001
+0.18
+9
1
000
0
0
0
000
0
0
0
001
-0.18
-9
0
010
-0.36
-18
0
011
-0.54
-27
0
100
-0.72
-36
0
101
-0.90
-45
0
110
-1.08
-54
0
111
-1.25
-63
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA), which is used
to set the coarse FSO, uses a switched-capacitor
CMOS technology and contains eight selectable gain
levels from 41 to 230, in increments of 27 (Table 2). The
output of the PGA is fed to the output summing junc-
tion. The three PGA gain bits A2, A1, and A0 are stored
in the configuration register.
Output Summing Junction
The third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and the offset TC correction. Both the offset and the off-
set TC correction voltages are gained by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset
sign bit and offset TC sign bit are stored in the configu-
ration register. The offset sign bit determines if the off-
set correction voltage is added to (sign bit is high) or
subtracted from (sign bit is low) the PGA output.
Negative offset TC errors require a logic high for the
offset TC sign bit. Alternately, positive offset TC errors
dictate a logic low for the offset TC sign bit. The output
of the summing junction is fed to the output buffer.
Table 2. PGA Gain Settings and IRO DAC
Step Size
PGA
VALUE
A2
A1
A0
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
PGA
GAIN
(V/V)
41
68
95
122
149
176
203
230
OUTPUT-
REFERRED IRO
DAC STEP SIZE
(V_DD = 5V) (V)
0.369
0.612
0.855
1.098
1.341
1.584
1.827
2.070
Output Buffer
OUT can drive 0.1µF of capacitance. If CS is brought
low, OUT becomes high impedance (resulting in typical
output impedance of 1MΩ). The output is current limit-
ed and can be shorted to either V_DD or V_SS indefinitely.
The maximum output voltage can be limited using the
LIMIT pin. Output limiting can be performed for sensor
diagnostic purposes. Connect LIMIT to V_DD to disable
the voltage-limiting feature.
Bridge Drive
Fine FSO correction is accomplished by varying the
sensor excitation current with the 12-bit FSO DAC
(Figure 3). Sensor bridge excitation is performed by a
programmable current source capable of delivering up
to 2mA. The reference current at ISRC is established by
resistor R_ISRC and by the voltage at node ISRC (con-
trolled by the FSO DAC). The reference current flowing
through this pin is multiplied by a current mirror (AA ≅
14) and then made available at BDRIVE for sensor exci-
tation. Modulation of this current with respect to tem-
perature can be used to correct FSOTC errors, while
modulation with respect to the output voltage (V_OUT)
can be used to correct FSO linearity errors.
Digital-to-Analog Converters
The four 12-bit, sigma-delta DACs typically settle in
less than 100ms. The four DACs have a corresponding
memory register in EEPROM for storage of correction
coefficients.
Use the FSO DAC for fine FSO adjustments. The FSO
DAC takes its reference from V_DD and controls V_ISRC
which, in conjunction with R_ISRC, sets the baseline sen-
sor excitation current. The Offset DAC also takes its ref-
erence from V_DD and provides a 1.22mV resolution with
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