MAX1213N Datasheet, PDF (8/21 Pages) Maxim Integrated Products – 1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications

1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
PIN
1, 6, 11–14, 20,
25, 62, 63, 65
2, 5, 7, 10, 15, 16,
18, 19, 21, 24,
64, 66, 67
3
4
8
9
17
22
23
26, 45, 61
27, 28, 41, 44, 60
29
30
31
32
33
34
35
36
NAME
AV_CC
AGND
REFIO
REFADJ
INP
INN
CLKDIV
CLKP
CLKN
OGND
OV_CC
D0N
D0P
D1N
D1P
D2N
D2P
D3N
D3P
Pin Description
FUNCTION
Analog Supply Voltage. Bypass AV_CC to AGND with a parallel combination of 0.1µF and 0.22µF
capacitors for best decoupling results. Connect all AV_CC inputs together. See the Grounding,
Bypassing, and Board Layout Considerations section.
Analog Converter Ground. Connect all AGND inputs together.
Reference Input/Output. Pull REFADJ high to allow REFIO to accept an external reference.
Pull REFADJ low to activate the internal 1.24V-bandgap reference. Connect a 0.1µF capacitor
from REFIO to AGND for both internal and external reference.
Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases
FSR). Connect REFADJ to AV_CC to override the internal reference with an external source
connected to REFIO. Connect REFADJ to AGND to allow the internal reference to determine the
FSR of the data converter. See the FSR Adjustment Using the Internal Bandgap Reference
section.
Positive Analog Input Terminal. Internally self-biased to 0.74V.
Negative Analog Input Terminal. Internally self-biased to 0.74V.
Clock Divider Input. CLKDIV controls the sampling frequency relative to the input clock
frequency. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: Sampling frequency is at one-half the input clock frequency.
CLKDIV = 1: Sampling frequency is equal to the input clock frequency.
True Clock Input. Apply an LVDS-compatible input level to CLKP. Internally self-biased to
1.15V.
Complementary Clock Input. Apply an LVDS-compatible input level to CLKN. Internally self-
biased to 1.15V.
Digital Converter Ground. Ground connection for digital circuitry and output drivers. Connect all
OGND inputs together.
Digital Supply Voltage. Bypass OV_CC with a 0.1µF capacitor to OGND. Connect all OV_CC inputs
together. See the Grounding, Bypassing, and Board Layout Considerations section.
Complementary Output Bit 0 (LSB)
True Output Bit 0 (LSB)
Complementary Output Bit 1
True Output Bit 1
Complementary Output Bit 2
True Output Bit 2
Complementary Output Bit 3
True Output Bit 3
8 _______________________________________________________________________________________