MAX1213N Datasheet, PDF (10/21 Pages) Maxim Integrated Products – 1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications

1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
AV_CC
OV_CC
INP
INN
REFIO
REFADJ
CLKP
CLKN
CLKDIV
T/H
900Ω
900Ω
COMMON-
MODE
BUFFER
REFERENCE
DIV1/DIV2
12-BIT PIPELINE
ADC
CLOCK
MANAGEMENT
MAX1213N
LVDS
DATA
PORT
DCLKP
DCLKN
D0P/N
D1P/N
D2P/N
D11P/N
ORP/ORN
T/B
AGND
Figure 1. Block Diagram
OGND
Detailed Description—
Theory of Operation
The MAX1213N uses a fully differential pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy, and linearity while minimizing power
consumption.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a 0.74V com-
mon-mode voltage, and accept a differential analog
input voltage swing of ±V_FS / 4 each, resulting in a typi-
cal 1.38V_P-P differential full-scale signal swing. Inputs
INP and INN are sampled when the differential sampling
clock signal transitions high. When using the clock-
divide mode, the analog inputs are sampled at every
other high transition of the differential sampling clock.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in user-selectable two’s-complement
or offset binary output formats with LVDS-compatible
output levels. See Figure 1 for a more detailed view of
the MAX1213N architecture.
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