MAX1213N Datasheet, PDF (12/21 Pages) Maxim Integrated Products – 1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications

1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
REFT
ADC FULL SCALE = REFT - REFB
REFERENCE
REFB
1V
BUFFER
CONTROL LINE TO
DISABLE REFERENCE BUFFER
AV_CC
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
REFERENCE-
SCALING AMPLIFIER
G
AV_CC / 2
MAX1213N
REFIO
REFADJ*
0.1µF
100Ω*
*REFADJ MAY
BE SHORTED TO
AGND DIRECTLY.
Figure 3. Simplified Reference Architecture
On-Chip Reference Circuit
The MAX1213N features an internal 1.24V-bandgap refer-
ence circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the FSR
of the MAX1213N. Bypass REFIO with a 0.1µF capacitor
to AGND. To compensate for gain errors or increase/de-
crease the ADC’s FSR, the voltage of this bandgap refer-
ence can be indirectly adjusted by adding an external
resistor (e.g., 100kΩ trim potentiometer) between
REFADJ and AGND or REFADJ and REFIO. See the
Applications Information section for a detailed description
of this process.
To disable the internal reference, connect REFADJ to
AV_CC. Apply an external, stable reference to set the
converter’s full scale. To enable the internal reference,
connect REFADJ to AGND.
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX1213N with an LVDS-
or LVPECL-compatible clock to achieve the best dynam-
ic performance. The clock signal source must be of high
quality and low phase noise to avoid any degradation in
the noise performance of the ADC. The clock inputs
(CLKP, CLKN) are internally biased to 1.15V and accept
a typical 0.5V_P-P differential signal swing (Figure 4). See
the Differential, AC-Coupled LVPECL-Compatible Clock
Input section for more circuit details on how to drive
CLKP and CLKN appropriately. Although not recom-
mended, the clock inputs also accept a single-ended
input signal.
CLKP
CLKN
AV_DD
2.89kΩ
5.35kΩ
5.35kΩ
5.35kΩ
AGND
Figure 4. Simplified Clock Input Architecture
The MAX1213N also features an internal clock-man-
agement circuit (duty-cycle equalizer) that ensures the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal
that desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum 20MHz
clock frequency to allow the device to meet data sheet
specifications.
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