MAX1204_12 Datasheet, PDF (8/23 Pages) Maxim Integrated Products – 5V, 8-Channel, Serial, 10-Bit ADC with 3V Digital Interface

MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
DOUT
+3.3V
3kΩ
DOUT
3kΩ
C_LOAD
C_LOAD
GND
GND
a. High-Z to V_OH and V_OL to V_OH
b. High-Z to V_OL and V_OH to V_OL
Figure 1. Load Circuits for Enable Time
+3.3V
DOUT
3kΩ
DOUT
3kΩ
GND
C_LOAD
C_LOAD
GND
a. V_OH to High-Z
b. V_OL to High-Z
Figure 2. Load Circuits for Disable Time
_______________Detailed Description
The MAX1204 uses a successive-approximation con-
version technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to 3V
microprocessors (µPs). Figure 3 is the MAX1204 block
diagram.
Pseudo-Differential Input
Figure 4 shows the analog-to-digital converter’s
(ADC’s) analog comparator’s sampling architecture. In
single-ended mode, IN+ is internally switched to
CH0–CH7 and IN- is switched to GND. In differential
mode, IN+ and IN- are selected from pairs of CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels using Tables 3 and 4.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable with-
in ±0.5 LSB (±0.1 LSB for best results) with respect to
CS ¹⁸
SCLK ¹⁹
DIN ¹⁷
SHDN ¹⁰
CH0 ¹
CH1 ²
CH2 ³
CH3 ⁴
CH4 ⁵
CH5 ⁶
CH6 ⁷
CH7 ⁸
GND ¹³
REFADJ ¹²
REF ¹¹
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
T/H
CLOCK
IN _SAR
ADC
OUT
REF
+2.44V
REFERENCE
A ≈ 1.68
20k
MAX1204
+4.096V
15 _DOUT
16 _SSTRB
20 _VDD
14 _VL
9
V_SS
Figure 3. Block Diagram
GND during a conversion. To do this, connect a 0.1µF
capacitor from IN- (of the selected analog input) to
GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C_HOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on C_HOLD as a
sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C_HOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(V_IN+) - (V_IN-)] from C_HOLD to the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
8
Maxim Integrated