MAX1204_12 Datasheet, PDF (12/23 Pages) Maxim Integrated Products – 5V, 8-Channel, Serial, 10-Bit ADC with 3V Digital Interface

MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and
conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS on the MAX1204 low.
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB3.
6) Pull CS on the MAX1204 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with one leading zero, two trailing sub-bits (S1 and S0),
and three trailing zeros. Total conversion time is a func-
tion of the serial clock frequency and the amount of idle
time between 8-bit transfers. To avoid excessive T/H
droop, make sure that the total conversion time does
not exceed 120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 15); for bipolar inputs, the output is two’s-
complement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format. The digital output logic
level is adjusted with the V_L pin. This allows DOUT and
SSTRB to interface with 3V logic without the risk of
overdrive. The MAX1204’s digital inputs are designed
to be compatible with 3V CMOS logic as well as 5V
logic.
Internal and External Clock Modes
The MAX1204 can use either an external serial clock
or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1204.
The T/H acquires the input signal as the last three bits
of the control byte are clocked into DIN. Bits PD1 and
PD0 of the control byte program the clock mode.
Figures 7–10 show the timing characteristics common
to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time or
droop on the sample-and-hold can degrade conversion
results. Use internal clock mode if the clock period
exceeds 10µs or if serial-clock interruptions could cause
the conversion interval to exceed 120µs.
Internal Clock
In internal clock mode, the MAX1204 generates its own
conversion clock. This frees the µP from running the
SAR conversion clock, and allows the conversion
results to be read back at the processor’s convenience,
at any clock rate from zero to 2MHz. SSTRB goes low
at the start of the conversion, then goes high when the
conversion is complete. SSTRB is low for a maximum of
10µs, during which time SCLK should remain low for
best noise performance. An internal register stores data
while the conversion is in progress. SCLK clocks the
data out at this register at any time after the conversion
is complete. After SSTRB goes high, the next falling
clock edge produces the MSB of the conversion at
DOUT, followed by the remaining bits in MSB-first for-
mat (Figure 9). CS does not need to be held low once a
conversion is started. Pulling CS high prevents data
from being clocked into the MAX1204 and three-states
DOUT, but it does not adversely affect an internal
clock-mode conversion already in progress. When
internal clock mode is selected, SSTRB does not go
high impedance when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. Data can be shifted in and out of the MAX1204 at
clock rates up to 2.0MHz if the acquisition time, t_ACQ, is
kept above 1.5µs.
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Maxim Integrated