MAX11359A Datasheet, PDF (8/66 Pages) Maxim Integrated Products – 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = DV_DD = +1.8V to +3.6V, V_REF = +1.25V, external reference, CLK32K = 32.768kHz (external clock), C_REG = 10µF, C_CPOUT =
10µF, 10µF between CF+ and CF-, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
DV_DD Monitor Turn-On Time
CPOUT Monitor Supply Voltage
Range
CPOUT Monitor Trip Threshold
CPOUT Monitor Hysteresis
CPOUT Monitor Turn-On Time
Internal Power-On Reset Voltage
32kHz Oscillator (32KIN, 32KOUT)
Clock Frequency
DV_DD = 2.7V
Stability
DV_DD = 1.8V to 3.6V, excluding crystal
Oscillator Startup Time
Crystal Load Capacitance
LOW-FREQUENCY CLOCK INPUT/OUTPUT (CLK32K)
Output Clock Frequency
Absolute Input to Output Clock
Jitter
Cycle to cycle
Input to Output Rise/Fall Time
10% to 90%, 30pF load
Input Duty Cycle
Output Duty Cycle
HIGH-FREQUENCY CLOCK OUTPUT (CLK)
f_OUT = f_FLL
FLL Output Clock Frequency
f_OUT = f_FLL/2, power-up default
f_OUT = f_FLL/4
f_OUT = f_FLL/8
Absolute Clock Jitter
Cycle to cycle, FLL off
Cycle to cycle, FLL on
Rise and Fall Time
t_R/t_F 10% to 90%, 30pF load
Duty Cycle
f_OUT = 4.9152MHz
f_OUT = 2.4576MHz, 1.2288MHz, 614.4kHz
Uncalibrated CLK Frequency
Error
FLL calibration not performed
DIGITAL INPUTS (SCLK, DIN, CS, UPIO_, CLK32K)
Input High Voltage
V_IH
Input Low Voltage
V_IL
MIN TYP MAX UNITS
5
ms
1.0
3.6
V
2.7
2.8
2.9
V
35
mV
5
ms
1.7
V
32.768
25
1500
6
kHz
ppm
ms
pF
32.768
kHz
5
ns
5
ns
40
60
%
43
%
4.8660
2.4330
1.2165
608.25
40
45
4.9152
2.4576
1.2288
614.4
0.15
1
4.9644
2.4822
1.2411
620.54
10
60
55
±35
MHz
kHz
ns
ns
%
%
0.7 x
DV_DD
V
0.3 x
DV_DD
V
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