MAX1090 Datasheet, PDF (8/20 Pages) Maxim Integrated Products – 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface

400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
PIN
NAME
MAX1090 MAX1092
1
1
HBEN
2
2
D7
3
3
D6
4
4
D5
5
5
D4
6
6
D3
7
7
D2
8
8
D1/D9
9
9
D0/D8
10
10
INT
11
11
RD
12
12
WR
13
13
CLK
14
14
CS
15
—
CH7
16
—
CH6
17
—
CH5
18
—
CH4
19
15
CH3
20
16
CH2
21
17
CH1
22
18
CH0
23
19
COM
24
20
GND
25
21
REFADJ
26
22
REF
27
23
V_DD
28
24
V_LOGIC
FUNCTION
High Byte Enable. Used to multiplex the 10-bit conversion result.
1: 2 MSBs are multiplexed on the data bus.
0: 8 LSBs are available on the data bus.
Three-State Digital I/O Line (D7)
Three-State Digital I/O Line (D6)
Three-State Digital I/O Line (D5)
Three-State Digital I/O Line (D4)
Three-State Digital I/O Line (D3)
Three-State Digital I/O Line (D2)
Three-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
Three-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
INT goes low when the conversion is complete and the output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD will enable the read operation on
the data bus.
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
In internal clock mode, connect this pin to either V_DD or GND.
Active-Low Chip Select. When CS is high, digital outputs (INT, D7–D0) are high impedance.
Analog Input Channel 7
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to ±0.5LSB during conversion.
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01µF
capacitor. When using an external reference, connect REFADJ to V_DD to disable the internal
bandgap reference.
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND
when using the internal reference.
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
Digital Power Supply. V_LOGIC powers the digital outputs of the data converter and can range
from +2.7V to V_DD + 300mV.
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