MAX1090 Datasheet, PDF (5/20 Pages) Maxim Integrated Products – 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface

400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS (continued)
(V_DD = V_LOGIC = +5V ±10%, COM = GND, REFADJ = V_DD, V_REF = +2.5V, 4.7µF capacitor at REF pin, f_CLK = 7.6MHz (50% duty
cycle), T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
CS Rise to Output Disable
RD Rise to Output Disable
RD Fall to Output Data Valid
HBEN Rise to Output Data Valid
HBEN Fall to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
SYMBOL
t_TC
t_TR
t_DO
t_DO1
t_DO1
t_INT1
t_DO2
CONDITIONS
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
C_LOAD = 20pF, Figure 1
MIN TYP MAX UNITS
10
60
ns
10
40
ns
10
50
ns
10
50
ns
10
80
ns
50
ns
100
ns
Note 1: Tested at V_DD = +5V, COM = GND, unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V_DD.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
DOUT
3k
C_LOAD
20pF
V_LOGIC
3k
DOUT
C_LOAD
20pF
a) HIGH-Z TO V_OH AND V_OL TO V_OH
b) HIGH-Z TO V_OL AND V_OH TO V_OL
Figure 1. Load Circuits for Enable/Disable Times
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