MAX1090 Datasheet, PDF (13/20 Pages) Maxim Integrated Products – 400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface

400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
can be used. At power-up, the MAX1090/MAX1092
enter the default external clock mode.
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. To select
this mode, bit D7 of the control byte must be set to 1
and bit D6 must be set to 0; the internal clock frequen-
cy is then selected, resulting in a 3.6µs conversion
time. When using the internal clock mode, connect the
CLK pin either high or low to prevent the pin from float-
ing.
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to one. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. Proper operation requires a 100kHz to
7.6MHz clock frequency with 30% to 70% duty cycle.
Operating the MAX1090/MAX1092 with clock frequen-
CLK
WR
t_CWH
CLK
ACQUISITION STARTS _{ACQUISITION ENDS}
t_CP
CONVERSION STARTS
t_CWS ^tCH
t_CL
ACQMOD = "0"
ACQUISITION STARTS
WR GOES HIGH WHEN CLK IS HIGH.
ACQUISITION ENDS
CONVERSION STARTS
WR
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS LOW.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
t_DH
WR
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS HIGH.
t_CWS
ACQMOD = "0"
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
t_DH
WR
ACQMOD = "1"
t_CWH
WR GOES HIGH WHEN CLK IS LOW. ACQMOD = "0"
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
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