MAX1084 Datasheet, PDF (8/16 Pages) Maxim Integrated Products – 400ksps/300ksps, Single-Supply, Low-Power, Serial 10-Bit ADCs with Internal Reference

400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
DOUT
6k
DGND
a) HIGH-Z TO V_OH AND V_OL TO V_OH
Figure 1. Load Circuits for DOUT Enable Time
C_LOAD = 20pF
V_DD
6k
DOUT
C_LOAD = 20pF
DGND
b) HIGH-Z TO V_OL AND V_OH TO V_OL
DOUT
6k
C_LOAD = 20pF
DGND
a) V_OH TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
V_DD
DOUT
b) V_OLTO HIGH-Z
6k
C_LOAD = 20pF
DGND
_______________Detailed Description
Converter Operation
The MAX1084/MAX1085 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 10-bit output.
Figure 3 shows the MAX1084/MAX1085 in their simplest
configuration. The internal reference is trimmed to 2.5V.
The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1084/MAX1085 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current to 2µA (typ); pulling SHDN high
puts the device into operational mode. Pulling CS low ini-
tiates a conversion that is driven by SCLK. The conver-
sion result is available at DOUT in unipolar serial format.
The serial data stream consists of three zeros, followed
by the data bits (MSB first). All transitions on DOUT
occur 20ns after the rising edge of SCLK. Figures 8 and
9 show the interface timing information.
Analog Input
Figure 4 shows the sampling architecture of the ADC’s
comparator. The full-scale input voltage is set by the
internal reference (V_REF = +2.5V).
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor C_HOLD. Bringing CS low ends the acquisition
interval. At this instant, the T/H switches the input side
of C_HOLD to GND. The retained charge on C_HOLD repre-
sents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 10-
bit resolution. This action is equivalent to transferring a
charge from C_HOLD to the binary-weighted capacitive
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