DS21Q50 Datasheet, PDF (8/87 Pages) Maxim Integrated Products – Quad E1 Transceiver

Figure 1-1. Block Diagram
MCL
RECEIVE
SIDE
RRING1
RTIP1
VCO/PLL
TRANSMIT
SIDE
TRING1
TTIP1
TRANSCEIVER 1of 4
Parallel & Test Control Port
(routed to all blocks)
DS21Q50
User Outputs
Select
OUTA
OUTB
DATA
CLOCK
SYNC
Receive-Side
Framer
Elastic Store
And
IBO Buffer
RSER1
SYSCLK1
RSYNC1
DATA
CLOCK
SYNC
Sync
Control
IBO
Buffer
Transmit-Side
Formatter
Divide by
2/4/8
A
BU Ck
MUX
B
C
TRANSMIT
CLOCK SOURCE
A
Tx Ck
MUX ^B
LOTC
Detect
Backup Clock MUX
Transceivers 2, 3, and 4
RCLK Transceiver 2
RCLK Transceiver 3
RCLK Transceiver 4
SYSTEM
INTERFACE
MUX
TSYNC1
TSER1
TCLK1
Alternate
Jitter
Attenuator
4/8/16MHz
Synthesizer
REFCLK
4/8/16MCK
8 of 87