DS21Q50 Datasheet, PDF (48/87 Pages) Maxim Integrated Products – Quad E1 Transceiver

DS21Q50
11. IDLE CODE INSERTION
The transmit idle registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten
with the code placed in the transmit idle-definition register (TIDR). This allows the same 8-bit code to be
placed into any of the 32 E1 channels.
Each of the bit positions in the TIRs represents a DS0 channel in the outgoing frame. When these bits are
set to 1, the corresponding channel transmits the idle code contained in the TIDR.
Register Name:
Register Description:
Register Address:
TIR1, TIR2, TIR3, TIR4
Transmit Idle Registers
24 Hex, 25 Hex, 26 Hex, 27 Hex
Bit
Name
Name
Name
Name
7
CH8
CH16
CH24
CH32
6
CH7
CH15
CH23
CH31
5
CH6
CH14
CH22
CH30
4
CH5
CH13
CH21
CH29
3
CH4
CH12
CH20
CH28
2
CH3
CH11
CH19
CH27
1
CH2
CH10
CH18
CH26
0
CH1
CH9
CH17
CH25
NAME
CH1 to CH32
BIT
TIR1.0 to 4.7
FUNCTION
Transmit Idle Code-Insertion Control Bits
0 = do not insert the idle code in the TIDR into this channel
1 = insert the idle code in the TIDR into this channel
Register Name:
Register Description:
Register Address:
TIDR
Transmit Idle Definition Register
23 Hex
Bit
7
6
5
4
3
Name TIDR7 TIDR6 TIDR5 TIDR4 TIDR3
2
TIDR2
1
TIDR1
0
TIDR0
NAME
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
BIT
FUNCTION
7
MSB of the idle code (this bit is transmitted first)
6
5
4
3
2
1
0
LSB of the idle code (this bit is transmitted last)
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