DS21Q50 Datasheet, PDF (32/87 Pages) Maxim Integrated Products – Quad E1 Transceiver

DS21Q50
5. STATUS AND INFORMATION REGISTERS
A set of four registers—status register 1 (SR1), status register 2 (SR2), receive information register (RIR),
and synchronizer status register (SSR)—contains information about the DS21Q50 framer’s real-time
status
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
sets to 1. The bits in the SR1, SR2, and RIR1 registers operate in a latched fashion. The SSR contents are
not latched. This means that if an event or an alarm occurs and a bit is set to 1 in any of the registers, it
remains set until the user reads that bit. The bit is cleared when it is read and it is not set again until the
event has occurred again (or in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit remains set
if the alarm is still present).
The user always precedes a read of the SR1, SR2, and RIR registers with a write. The byte written to the
register informs the framer which bits the user wishes to read and have cleared. The user writes a byte to
one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he
or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read
register is updated with the latest information. When a 0 is written to a bit position, the read register is not
updated and the previous value is held. A write to the status and information registers is immediately
followed by a read of the same register. The read result should be logically ANDed with the mask byte
that was just written and this value should be written back into the same register to ensure that bit clears.
This second write step is necessary because the alarms and events in the status registers occur
asynchronously in respect to their access through the parallel port. The write-read-write scheme allows an
external microcontroller or microprocessor to individually poll certain bits without disturbing the other
bits in the register. This operation is key in controlling the DS21Q50 with higher order software
languages.
The SSR register operates differently than the other three. It is a read-only register and reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1and SR2 registers can initiate a hardware interrupt through the INT output pin. Each of the
alarms and events in SR1 and SR2 can be either masked or unmasked from the interrupt pin through the
interrupt mask register 1 (IMR1) and interrupt mask register 2 (IMR2).
The interrupts caused by alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently than the
interrupts caused by events in SR1 and SR2 (namely RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC,
TAF, LOTC, and RCMF). The alarm-caused interrupts force the INT pin low whenever the alarm
changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 5-1). The
INT pin is allowed to return high (if no other interrupts are present) when the user reads the alarm bit that
caused the interrupt to occur even if the alarm is still present.
The event-based interrupts force the INT pin low when the event occurs. The INT pin returns high ()
when the user reads the event bit that caused the interrupt to occur. Furthermore, some event-based
interrupts occur continuously as long as the event is occurring (RSLIP, SEC, TMF, RMF, TAF, RAF,
RCMF). Other event-based interrupts force the INT pin low only once when the event is first detected
(LOTC, PRSBD, RDMA, RSA1, RSA0), i.e., the PRBSD interrupt fires once when the receiver detects
the PRBS pattern. If the receiver continues to receive the PRBS pattern, no more interrupts fire. If the
receiver then detects that PRBS is no longer being sent, the receiver resets and when it receives the PRBS
pattern again, another interrupt fires.
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