MAX16000 Datasheet, PDF (7/26 Pages) Maxim Integrated Products – Low-Voltage, Quad-/Hex-/Octal-Voltage μP Supervisors

Low-Voltage, Quad-/Hex-/Octal-Voltage
µP Supervisors
Pin Description (MAX16000/MAX16001/MAX16002)
PIN
NAME
FUNCTION
1
1
1
2
2
2
3
4
4
4
5
5
5 6—
6 7—
7 10 8
8 11 —
9 12 —
10 14 10
11 15 11
12 16 12
—3
3
—8
6
—9
7
— 13 9
—— —
IN3
IN4
GND
V_CC
OUT3
OUT4
MARGIN
OUT2
OUT1
IN1
IN2
TOL
WDI
MR
SRT
RESET
EP
Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
Ground
Unmonitored Power-Supply Input
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the
voltage at IN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the
voltage at IN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state),
regardless of the voltage at any monitored input.
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the
voltage at IN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the
voltage at IN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL
to V_CC to select 10% threshold tolerance.
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period,
RESET is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on
WDI is detected. The watchdog timer enters a startup period that allows 54s for the first
transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The
WDI floating-state detector uses a small 400nA current. Therefore, do not connect WDI to
anything that will source or sink more than 200nA. Note that the leakage current specification for
most three-state drivers exceeds 200nA.
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the
reset timeout period after MR is deasserted. MR is pulled up to V_CC through a 20kΩ resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period.
The reset timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10⁶ (Ω) x C_SRT (F). For the internal timeout period of 140ms (min),
connect SRT to V_CC.
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its
respective threshold or MR is asserted. RESET remains asserted for the reset timeout period
after all monitored voltages exceed their respective thresholds and MR is deasserted. This
open-drain output has a 30µA internal pullup.
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a
low thermal resistance path from the IC junction to the PCB. Do not use as the electrical
connection to GND.
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