MAX16000 Datasheet, PDF (20/26 Pages) Maxim Integrated Products – Low-Voltage, Quad-/Hex-/Octal-Voltage μP Supervisors

Low-Voltage, Quad-/Hex-/Octal-Voltage
µP Supervisors
V_CC = 3.3V
5V
100kΩ
V_CC
V_CC
OUT_
RESET
MAX16001/
MAX16002/
MAX16004–MAX16007
GND
GND
IN_
V_{TH_}
RESET
OUT_
10%
t_RD
10%
t_D
V_{TH_}
90%
t_RP
90%
t_D
Figure 11. Interfacing to a Different Logic Supply Voltage
Figure 12. Output Timing Diagram
RESET Output (MAX16001/MAX16002/
MAX16004–MAX16007)
RESET asserts low when any of the monitored voltages
fall below their respective thresholds or MR is asserted.
RESET remains asserted for the reset timeout period
after all monitored voltages exceed their respective
thresholds and MR is deasserted (see Figure 12). This
open-drain output has a 30µA internal pullup. An exter-
nal pullup resistor to any voltage from 0 to 5.5V overrides
the internal pullup if interfacing to different logic supply
voltages. Internal circuitry prevents reverse current flow
from the external pullup voltage to V_CC (Figure 11).
WDO (MAX16005 Only)
WDO asserts and stays low whenever any of the IN_
inputs fall below their respective thresholds. WDO
deasserts without a timeout delay when all the IN_
inputs rise above their thresholds. When all the IN_
inputs rise above their thresholds, WDO asserts low
whenever the watchdog timer times out. WDO
deasserts after a valid WDI transition or if MR is pulled
low. The watchdog timer begins counting after the reset
timeout period once MR goes high. Pull MARGIN low to
deassert WDO regardless of any other condition. The
watchdog timer continues to run when MARGIN is low
and if a timeout occurs. WDO will assert MR after
MARGIN is deasserted. This open-drain output has a
30µA internal pullup. An external pullup resistor to any
voltage from 0 to 5.5V overrides the internal pullup if
interfacing to different logic supply voltages. Internal cir-
cuitry prevents reverse current flow from the external
pullup voltage to V_CC (Figure 11).
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