MAX15500 Datasheet, PDF (7/27 Pages) Maxim Integrated Products – Industrial Analog Current/Voltage-Output Conditioners

Industrial Analog Current/
Voltage-Output Conditioners
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +24V, VAVSS = -24V, VDVDD = 5.0V, CLOAD = 1nF, CCOMP = 0nF, VREFIN = 4.096V for the MAX15500, VREFIN = 2.5V for
the MAX15501. All specifications for TA = -40NC to +105NC. Typical values are at TA = +25NC, unless otherwise noted.)
PARAMETER
TIMING CHARACTERISTICS
Serial-Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS_ Fall to SCLK Fall Setup Time
SCLK Fall to CS_ Fall Hold Time
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Fall to DOUT Settle Time
SCLK Fall to DOUT Hold Time
SCLK Fall to DOUT Disable
SCLK Fall to READY Fall
CS_ Fall to DOUT Enable
CS_ Rise to DOUT Disable
CS_ Rise to READY Rise
CS_ Pulse-Width High
SYMBOL
CONDITIONS
fSCLK
tCH
tCL
tCSS
tCSH
tDS
tDH
tDOT
tDOH
tDOZ
tCR
tDOE
tCSDOZ
tCSR
tCSW
(Note 4)
40% duty cycle
60% duty cycle
To 1st SCLK falling edge
(Note 5)
CLOAD = 20pF
CLOAD = 0pF
14th SCLK deassertion (Note 6)
16th SCLK assertion, CLOAD = 0pF or 20pF
Asynchronous assertion
Asynchronous deassertion
Asynchronous deassertion, CLOAD = 20pF
MIN TYP MAX UNITS
0
20 MHz
20
ns
20
ns
15
ns
0
ns
15
ns
0
ns
30
ns
2
ns
30
ns
2
30
ns
1
35
ns
35
ns
35
ns
15
ns
Note 1: Use diodes as shown in the Typical Operating Circuit/Functional Diagram to ensure a voltage difference of 2V to 3.5V
from AVDD to AVDDO and from AVSS to AVSSO.
Note 2: RLOAD = 750I. For the MAX15500, RSENSE = 48.7I for FSMODE = DVDD and RSENSE = 42.2I for FSMODE = DGND.
For the MAX15501, RSENSE = 47.3I for FSMODE = DVDD and RSENSE = 41.2I for FSMODE = DGND. See the Typical
Operating Circuit/Functional Diagram.
Note 3: Condition at which part is stable.
Note 4: The maximum clock speed for daisy-chain applications is 10MHz.
Note 5: tCSH is applied to CS_ falling to determine the 1st SCLK falling edge in a free-running SCLK application. It is also applied
to CS_ rising with respect to the 15th SCLK falling edge to determine the end of the frame.
Note 6: After the 14th SCLK falling edge, the MAX15500/MAX15501 outputs are high impedance and DOUT data is ignored.
_______________________________________________________________________________________   7