MAX15500 Datasheet, PDF (25/27 Pages) Maxim Integrated Products – Industrial Analog Current/Voltage-Output Conditioners

Industrial Analog Current/
Voltage-Output Conditioners
Since the MAX15500/MAX15501 do not use a continuous
clock signal, the SPI read cycles are used to cycle the
error detection and reporting logic. Continue to poll the
device until the error readback reports an all clear status
when resolving single or multiple errors. See below for
examples of typical error handling situations and the
effects of the SPI read operations.
1) Error resolved by the system.
a) The MAX15500/MAX15501 detect an error condi-
tion and ERROR asserts.
b) The host controller reads the error register for the
first time. This has the effect of resetting ERROR.
The data indicates to the host processor which
error is active.
c) The host processor resolves the error successfully.
d) The host processor reads the error register for the
second time. The data still shows that the error is
present as the error persisted for some time after
step b and before step c. If the error is either an
open load or short circuit, the intermittent bit is set.
An overtemperature or a brownout does not set the
intermittent bit. Reading the register a second time
resets the register.
e) The host reads the error register for a third time.
The data now shows the error is resolved and
future occurrences of this error will trigger ERROR
assertion.
2) Error resolved before the host processor reads error
register.
a) The MAX15500/MAX15501 detect an error condi-
tion and ERROR asserts, but the error resolves
itself.
b) The host controller reads the error register for the
first time resetting ERROR. The data indicates to
the host processor which error is active. The data
also indicates to the host that the error has been
resolved since the intermittent bit is set.
c) The host processor reads the error register for the
second time. The data still shows that the error is
active. If the error is for an output fault, the data
also indicates to the host that the error has been
resolved since the intermittent bit is set. Reading
the register a second time resets the register.
3) An error that cannot be resolved.
a) The MAX15500/MAX15501 detect an error condi-
tion and ERROR asserts.
b) The host controller reads the error register for the
first time and resets ERROR. The data indicates to
the host processor which error is active.
c) The host processor takes action to resolve the
error unsuccessfully.
d) The host processor reads the error register for the
second time. The data still shows that the error is
present.
e) The host processor reads the error for the third
time. The data show the error to be unresolved.
ERROR does not respond to the same error until
the error is resolved and reported. ERROR asserts
if different errors occur.
Applications Information
Setting the Output Gain in Current Mode
In current mode, there is approximately 1.0V across the
current-sensing resistors at full scale. The current sens-
ing resistor sets the gain and is calculated as follows:
RSENSE = VSENSE_FS/IMAX
where VSENSE_FS is the full-scale voltage across the
sense resistor.
See Table 8 for values of VSENSE_FS.
Output Gain in Voltage Mode
The output gain in voltage mode is fixed as shown in
Table 9.
Selection of the Compensation
Capacitor (CCOMP)
Use Table 10 to select the compensation capacitor.
Layout Considerations
In the current-mode application, use Kelvin and a short
connection from SENSERN and SENSERP to the RSENSE
terminals to minimize gain-error drift. Balance and mini-
mize all analog input traces for optimum performance.
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