MAX154 Datasheet, PDF (7/12 Pages) Maxim Integrated Products – CMOS High-Speed 8-Bit ADCs with Multiplexer and Reference

CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
RD
500ns
1000ns
600ns
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
V_IN IS SAMPLED
AND THE FOUR MSBs
ARE LATCHED
V_IN IS TRACKED
BY INTERNAL
COMPARATORS
INT GOING LOW INDICATES
THAT CONVERSION IS
COMPLETE AND THAT
DATA CAN BE READ
Figure 4. Operating Sequence
Interface Mode 0
Figure 5 shows the timing diagram for Mode 0 opera-
tion. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extend-
ed to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
There are two status outputs: Interrupt (INT) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
device), is connected to the processor’s READY/WAIT
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
conversion result appears on the data outputs. If the
RDY output is not required, its external pull-up resistor
can be omitted. INT goes low when the conversion is
complete and returns high on the rising edge of CS or
RD.
Interface Mode 1
Mode 1 is designed for applications where the micro-
processor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a conversion (Figure 6). Data from the previous
conversion is immediately read from the outputs
(DB0–DB7).
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ oper-
ation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
CS
RD
ANALOG
CHANNEL
ADDRESS
RDY
INT
DATA
t_CSS
t_AS
ADDR
VALID
t_AH
t_RDY
t_CRD
HIGH IMPEDANCE
t_CSH
t_CSS
t_P
t_AS
ADDR
VALID
t_INTH
t_ACC2
t_DH
DATA
VALID
Figure 5. Mode 0 Timing Diagram
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