MAX14886 Datasheet, PDF (7/10 Pages) Maxim Integrated Products – Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter

Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
Detailed Description
The MAX14886 is a high-speed, low-skew, active
redriver multiplexer designed to switch and amplify
TMDS-formatted signals. Input buffers have 50I HDMI-
compliant terminations to VCC (see the Functional
Diagram/Truth Tables), allowing either DC-coupling to
an HDMI source or AC-coupling to a DisplayPort source.
Signals from the input buffers are multiplexed and
redriven by the limiting amplifier and an open-collector
output buffer. The HDMI monitor sink is DC-coupled to
the outputs and provides DC bias.
Both TMDS clock and data are multiplexed and redriven
to full HDMI v.1.4 levels with low skew and jitter to
guarantee mask compliance at an external HDMI con-
nector. The device is VESA DisplayPort Interoperability
Guideline v.1.1a-compliant and integrates seamlessly
with an external HDMI connector on the motherboard.
The low-frequency signals (DDC, CEC, and HPD) can be
handled by external low-cost logic.
The device accommodates differential inputs as low as
200mV and drives differential TMDS outputs to 1000mV
(typ). A precision resistor on the output level adjust pin
(ADJ) allows differential output back-termination resis-
tors of 400I (typ) to better meet HDMI mask jitter compli-
ance, while maintaining full TMDS swing requirements.
This device also features both active-high and active-
low enable inputs. One of the enable inputs can be
connected to either VCC or GND, while the other can be
used to control the device (see the Functional Diagram/
Truth Tables and Enable Inputs (EN1, EN2) section). This
eliminates any issues with logic sense and the need for
an inverter.
Level Translation
The device accepts two sets of four differential
DisplayPort-level TMDS-formatted inputs, each with
magnitudes as low as 200mV. The selected channel is
translated to full HDMI TMDS levels that are HDMI v.1.4
port mask-compliant up to 2.25Gbps.
Enable Inputs (EN1, EN2)
The device features both an active-high enable input
(EN1) and an active-low enable input (EN2) that can be
controlled by LVCMOS or LVTTL. EN1 has an internal
400kI (typ) pulldown resistor, and EN2 has an internal
400kI (typ) pullup resistor. When EN1 is driven low or
left unconnected, or EN2 is driven high or left uncon-
nected, the device enters low-power shutdown mode.
For normal operation drive both EN1 high and EN2 low.
See the Functional Diagram/Truth Tables.
Only one input is necessary to control the device. If
active-high enable is desired, connect EN2 to GND and
use EN1 to control the device. Similarly, for active-low
enable, connect EN1 to VCC and use EN2 to control the
device.
Note: The monitor sink termination must be present and
powered before enabling the device (see the Control
Sequence section and Figure 2).
Digital Control Input (SEL)
The device provides two sets of 4 channels for all the dif-
ferential signals required by HDMI connections. The SEL
input controls which channel is translated to the output
channel (see the Functional Diagram/Truth Tables). An
internal 400kI pulldown resistor guarantees that channel
A is translated to the output if the SEL pin is not externally
driven.
Output Level Adjust (ADJ)
The level-shifter’s output current and output signal swing
are set with an external ±1% precision 3.3kI (typ) resis-
tor. If a double output termination (400I typ) is desired
for signal integrity reasons, the ADJ resistor value can be
decreased to maintain a desired output swing (Figure 1).
Applications Information
HDMI Driver
The device’s high-speed, low-skew, active redriver
multiplexer is ideal for switching between outputs of
dual-graphics systems and signal conditioning to meet
HDMI v.1.4 compliance at an external HDMI connector
(Figure 1). It is well suited for switching between inte-
grated (e.g., Intel or AMD) and discrete graphics (e.g.,
NVIDIA or ATI GPU). The device is VESA DisplayPort
Interoperability Guideline v.1.1a-compliant (requires
external DDC logic) and integrates seamlessly with an
external HDMI connector on the motherboard.
Output Termination
Outputs are terminated in normal use by the HDMI moni-
tor. For 50I test equipment purposes, terminate each
output with a high-frequency bias-T that has an inductor
in series with a 50I resistor to VCC.
Control Sequence
The monitor sink termination must be present and pow-
ered before enabling the device. A simple circuit can
be added to protect the device by forcing hot-plug
detection (HPD) to be present before the part is enabled
(Figure 2).
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