MAX14886 Datasheet, PDF (5/10 Pages) Maxim Integrated Products – Dual DisplayPort Graphics Multiplexer with HDMI Level Shifter

Dual DisplayPort Graphics Multiplexer
with HDMI Level Shifter
Pin Configuration
TOP VIEW
30 29 28 27 26 25 24 23 22 21
VCC 31
20 D2CP
GND 32
19 D2CN
ADJ 33
18 D1CP
SEL 34
17 D1CN
GND 35
MAX14886
16 V_CC
V_CC 36
EN2 37
15 D0CP
14 D0CN
EN1 38
+
GND 39
*EP
13 CKCP
12 CKCN
V_CC 40
11 GND
1 2 3 4 5 6 7 8 9 10
*CONNECT EP TO GND.
TQFN
(5mm × 5mm × 0.75mm)
PIN
1
2
3
4
5, 10,
11, 21,
26, 32,
35, 39
6
7
8
9
12
13
14
15
16, 31,
36, 40
17
NAME
D0AP
D0AN
D0BP
D0BN
GND
CKAP
CKAN
CKBP
CKBN
CKCN
CKCP
D0CN
D0CP
VCC
D1CN
FUNCTION
Noninverting Input D0 for Channel A
Inverting Input D0 for Channel A
Noninverting Input D0 for Channel B
Inverting Input D0 for Channel B
Ground
Noninverting Input Clock for Channel A
Inverting Input Clock for Channel A
Noninverting Input Clock for Channel B
Inverting Input Clock for Channel B
Inverting Output Clock
Noninverting Output Clock
Inverting Output D0
Noninverting Output D0
Power-Supply Voltage. Bypass VCC
to GND with low-ESR 10nF and
4.7FF ceramic capacitors in parallel
as close as possible to the device.
Recommended on each VCC pin.
Inverting Output D1
Pin Description
PIN NAME
FUNCTION
18
D1CP Noninverting Output D1
19
D2CN Inverting Output D2
20
D2CP Noninverting Output D2
22
D2BP Noninverting Input D2 for Channel B
23
D2BN Inverting Input D2 for Channel B
24
D2AP Noninverting Input D2 for Channel A
25
D2AN Inverting Input D2 for Channel A
27
D1BP Noninverting Input D1 for Channel B
28
D1BN Inverting Input D1 for Channel B
29
D1AP Noninverting Input D1 for Channel A
30
D1AN Inverting Input D1 for Channel A
33
ADJ Output Level Adjust
34
SEL
Mux Select Input. SEL is internally
pulled down by a 400kI (typ) resistor.
Active-Low Enable Input. EN2 is inter-
37
EN2 nally pulled up by a 400kI (typ)
resistor.
Active-High Enable Input. EN1 is
38
EN1 internally pulled down by a 400kI (typ)
resistor.
—
EP Exposed Pad. Connect EP to GND.
5