MAX1407 Datasheet, PDF (7/48 Pages) Maxim Integrated Products – Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC

Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
TIMING CHARACTERISTICS (continued)
(MAX1407/MAX1408/MAX1409/MAX1414: AV_DD = DV_DD = 2.7V to 3.6V, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
TYPICAL TIMING PARAMETERS
CONDITIONS
OUT1/OUT2 Turn-Off Time
Input impedance > 1MΩ
(MAX1407/MAX1409/MAX1414 only)
Sleep Voltage Monitor Timeout
Period
t_DSLP
The delay for the sleep voltage monitor
output, RESET, to go high after AV_DD rises
above the reset threshold (+1.8V when bit
VM = 1 and +2.7V, when bit VM = 0); this is
largely driven by the startup of the 32kHz
oscillator
MIN TYP MAX
100
1.54
WU1 or WU2 Pulse Width
t_WU
Minimum pulse width required to detect a
wake-up event
1
Shutdown Deassert Delay
t_DPU
The delay for SHDN to go high after a valid
wake-up event
1
UNITS
µs
s
µs
µs
FOUT Turn-On Time
The turn-on time for the high-frequency
clock; it is gated by an AND function with
three signals—the RESET signal, the internal
t_DFON
low voltage V_DD monitor signal, and the
assertion of the PLL; the time delay is timed
31.25
ms
from when the low-voltage monitor trips or
the RESET going high, whichever happens
later; FOUT always starts in the low state
INT Delay
The delay for INT to go low after the FOUT
t_DFI
clock output has been enabled; INT is used
as an interrupt signal to inform the µP the
7.82
ms
high-frequency clock has started
FOUT Disable Delay
t_DFOF
The delay after a shutdown command has
asserted and before FOUT is disabled; this
gives the microcontroller time to clean up
and go into Sleep mode properly
1.95
ms
SHDN Assertion Delay
t_DPD
The delay after a shutdown command has
asserted and before SHDN is pulled low
(turning off the DC-DC converter) (Note 6)
2.93
ms
Note 1: Single conversion.
Note 2: DNL and INL are measured between code 010hex and 3FFhex.
Note 3: Offset error is referenced to code 010hex.
Note 4: Output swing is a function of external gain-setting feedback resistors and REF voltage.
Note 5: Measured with no load on FOUT, DOUT, and the DAC amplifiers. SCLK is idle, and all digital inputs are at DGND or DV_DD.
Note 6: SHDN stays high if the PLL is on.
Note 7: Actual worst-case performance is ±2.5LSB. Guaranteed limit of ±3.5LSB is due to production test limitation.
Note 8: Guaranteed by design. Not production tested.
_______________________________________________________________________________________ 7