MAX1407 Datasheet, PDF (20/48 Pages) Maxim Integrated Products – Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTC

Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
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FREQUENCY (Hz)
Figure 7. Frequency Response of the SINC³ Filter (Notch at
60Hz)
Figure 7 shows the filter frequency response. The
SINC³ characteristic cutoff frequency is 0.262 times the
first notch frequency. This results in a cutoff frequency
of 15.72Hz for a first filter notch frequency of 60Hz (out-
put data rate of 60Hz). The response shown in Figure 7
is repeated at either side of the digital filter’s sample
frequency (f_M) (f_M = 15.36kHz for 30Hz and f_M =
30.72kHz for 60Hz) and at either side of the related har-
monics (2f_M, 3f_M,....).
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. Therefore, for the plot of Figure 7
where the first notch of the filter is at 60Hz, the output
data rate is 60Hz. The notches of this (sinx/x)³ filter are
repeated at multiples of the first notch frequency. The
SINC³ filter provides an attenuation of better than
100dB at these notches.
For step changes at the input, enough settling time
must be allowed before valid data can be read. The
settling time depends upon the output data rate chosen
for the filter. The settling time of the SINC³ filter to a full-
scale step input can be up to four times the output data
period, or three times if the step change is synchrozied
with FSYNC.
Force/Sense DAC
(MAX1407/MAX1409/MAX1414)
The MAX1407/MAX1414 incorporate two 10-bit force/
sense DACs while the MAX1409 has one. The DACs
use a precise 1.25V internal bandgap reference for set-
ting the full-scale range. Program the DAC1 and DAC2
registers through the serial interface to set the output
voltages of the DACs seen at OUT1 and OUT2.
Shorting FB1(2) and OUT1(2) configures the DAC in a
unity-gain setting. Connecting resistors in a voltage-
divider configuration between OUT1(2), FB1(2), and
GND sets a different closed-loop gain for the output
amplifier (see the Applications Information section).
The DAC output amplifier typically settles to ±^1/2LSB
from a full-scale transition within 65µs, when it is con-
nected in unity gain and loaded with 12kΩ in parallel
with 200pF. Loads less than 2kΩ may degrade perfor-
mance. See the Typical Operating Characteristics sec-
tion for the source-and-sink capabilty of the DAC
output.
The MAX1407/MAX1409/MAX1414 feature a software-
programmable shutdown mode for the DACs that
reduce the total power consumption when they are not
used. The two DACs can be powered-down indepen-
dently or simultaneously by clearing the DA1E and
DA2E bits (see Power1 Register). DAC outputs OUT1
and OUT2 go high impedance when powered down.
The DACs are automatically powered up and ready for
a conversion when Idle or Run mode is entered.
Voltage Monitors
The MAX1407/MAX1408/MAX1409/MAX1414 include
two on-board voltage monitors. When AV_DD is below
the RESET trip threshold, RESET goes low and the RST
bit of the Status register is set to “1”. When AV_DD is
below the Low V_DD trip threshold, the LVD bit of the
Status register is set to 1.
RESET Voltage Monitor
The RESET voltage monitor is powered up at all times
(provided that VM = 0 and LVDE = 1 or VM = 1 and
LSDE = 1). A threshold voltage of either +1.8V or +2.7V
may be selected for the RESET voltage monitor (see
Power2 Register). At initial power-up, the RESET trip
threshold is set to 2.7V. If the RESET voltage monitor is
tripped, the RST bit of the status register is set to “1”
and RESET goes low. RESET is held low for 1.54
seconds (typ) after AV_DD rises above the RESET voltage
monitor threshold. If AV_DD is no longer below the RESET
threshold, reading the Status register will clear RST.
Low V_DD Voltage Monitor
When the device is operating in Run, Idle, or Standby
mode (see Power Modes) and AV_DD goes below +2.7V,
the low V_DD monitor trips, indicating that the supply volt-
age is below the safe minimum for proper operation.
When tripped, the Low V_DD Voltage Monitor sets the LVD
bit of the Status register to 1. If AV_DD is no longer below
+2.7V, reading the Status register will clear LVD. The low
V_DD monitor is powered down in Sleep mode. When it is
powered down, the LVD bit stays unchanged. The LVD is
cleared if it is read in Sleep mode.
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