MAX1401 Datasheet, PDF (7/36 Pages) Maxim Integrated Products – +3V, 18-Bit, Low-Power, Multichannel, Oversampling Sigma-Delta ADC

+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Note 16: These specifications apply to CLKOUT only when driving a single CMOS load.
Note 17: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate
correctly.
Note 18: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 19: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 20: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
When used with a resonator or crystal between CLKIN and CLKOUT, the actual power dissipation and I_DD in standby
mode will depend on the resonator or crystal type.
TIMING CHARACTERISTICS
(V+ = +2.7V to +3.6V, V_DD = +2.7V to +3.6V, AGND = DGND, f_CLKIN = 2.4576MHz, input logic 0 = 0V, logic 1 = V_DD, T_A = T_MIN to
T_MAX, unless otherwise noted.) (Notes 21, 22, 23)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Master Clock Frequency
Crystal oscillator or clock
X2CLK = 0
0.4
f_CLKIN
externally supplied for
specified performance
(Notes 24, 25)
X2CLK = 1
0.8
2.5
MHz
5.0
Master Clock Input Low Time f_{CLKIN LO} t_CLKIN = 1 / f_CLKIN, X2CLK = 0
0.4 ·
t_CLKIN
ns
Master Clock Input High Time f_{CLKIN HI} t_CLKIN = 1 / f_CLKIN, X2CLK = 0
0.4 ·
t_CLKIN
ns
INT High Time
X2CLK = 0, N = 2^{(2 · MF1 + MF0)}
t_INT
280 / N
· t_CLKIN
ns
X2CLK = 1, N = 2^{(2 · MF1 + MF0)}
560 / N
· t_CLKIN
RESET Pulse Width Low
t₂
100
ns
SERIAL-INTERFACE READ OPERATION
INT to CS Setup Time (Note 10)
t₃
0
ns
SCLK Setup to Falling Edge CS
t₄
30
ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t₅
30
ns
SCLK Falling Edge to Data Valid
Delay (Notes 26, 27)
t₆
0
100
ns
SCLK High Pulse Width
t₇
SCLK Low Pulse Width
t₈
CS Rising Edge to SCLK Rising
Edge Hold Time (Note 23)
t₉
100
ns
100
ns
0
ns
Bus-Relinquish Time After SCLK
Rising Edge (Note 28)
t₁₀
10
100
ns
SCLK Rising Edge to INT High
(Note 29)
t₁₁
ns
200
ns
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