MAX1400_02 Datasheet, PDF (7/34 Pages) Maxim Integrated Products – +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC

+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Note 16: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz exceeds 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 17: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 18: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
When used with a resonator or crystal between CLKIN and CLKOUT, the actual power dissipation and I_DD in standby
mode depends on the resonator or crystal type.
TIMING CHARACTERISTICS
(V+ = +5V ±5%, V_DD = +2.7V to +5.25V, AGND = DGND, f_CLKIN = 2.4576MHz; input logic 0 = 0V; logic 1 = V_DD, T_A = T_MIN to T_MAX,
unless otherwise noted.) (Notes 19, 20, 21)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Master Clock Frequency
Crystal oscillator or clock
X2CLK = 0
0.4
f_CLKIN
externally supplied for
specified performance
(Notes 22, 23)
X2CLK = 1
0.8
2.5
MHz
5.0
Master Clock Input Low Time f_{CLKIN LO} t_CLKIN = 1 / f_CLKIN, X2CLK = 0
0.4 x
t_CLKIN
ns
Master Clock Input High Time f_{CLKIN HI} t_CLKIN = 1 / f_CLKIN, X2CLK = 0
0.4 x
t_CLKIN
ns
INT High Time
X2CLK = 0, N = 2^{(2 x MF1 + MF0)}
t_INT
280 / N
x t_CLKIN
ns
X2CLK = 1, N = 2^{(2 x MF1 + MF0)}
560 / N
x t_CLKIN
RESET Pulse Width Low
t₂
100
ns
SERIAL-INTERFACE READ OPERATION
INT to CS Setup Time
t₃
(Note 8)
0
ns
SCLK Setup to Falling Edge CS
t₄
30
ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t₅
30
ns
SCLK Falling Edge to Data Valid
Delay (Notes 24, 25)
t₆
SCLK High Pulse Width
t₇
SCLK Low Pulse Width
t₈
CS Rising Edge to SCLK Rising
Edge Hold Time
t₉
V_DD = 5V
V_DD = 3.3V
(Note 21)
0
80
ns
0
100
100
ns
100
ns
0
ns
Bus Relinquish Time After SCLK
Rising Edge (Note 26)
t₁₀
SCLK Rising Edge to INT High
(Note 27)
t₁₁
V_DD = 5V
V_DD = 3.3V
V_DD = 5V
V_DD = 3.3V
10
70
ns
10
100
100
ns
200
ns
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