MAX1400_02 Datasheet, PDF (17/34 Pages) Maxim Integrated Products – +5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC

+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Analog Inputs AIN1 to AIN6
Inputs AIN1 and AIN2 map to transfer-function register
1, regardless of scanning mode (SCAN = 1) or single-
ended vs. differential (DIFF) modes. Likewise, AIN3 and
AIN4 inputs always map to transfer-function register 2.
Finally, AIN5 always maps to transfer-function register 3
(input AIN6 is analog common).
CALGAIN and CALOFF
When not in scan mode (SCAN = 0), A1 and A0 select
which transfer function applies to CALGAIN and
CALOFF. In scan mode (SCAN = 1), CALGAIN and
CALOFF are always mapped to transfer-function regis-
ter 3. Note that when scanning while M1 ≠ M0, the scan
sequence includes both CALGAIN and CALOFF chan-
nels (Table 4). CALOFF always precedes CALGAIN,
even though both channels share the same channel ID
tag (Table 11).
Note that changing the status of any active channel
control bits will cause INT to immediately transition high
and the modulator/filter to be reset. INT will reassert
after the appropriate digital-filter settling time. The con-
trol settings of the inactive channels may be changed
freely without affecting the status of INT or causing the
filter/modulator to be reset.
PGA Gain
Bits G2–G0 control the PGA gain according to Table 6.
Unipolar/Bipolar Mode
The U/B bit places the channel in either bipolar or
unipolar mode. A 0 selects bipolar mode, and a 1
selects unipolar mode. This bit does not affect the ana-
log-signal conditioning. The modulator always accepts
bipolar inputs and produces a bitstream with 50%
ones-density when the selected inputs are at the same
potential. This bit controls the processing of the digital-
filter output, such that the available output bits are
Table 6. PGA Gain Codes
G2
G1
G0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PGA GAIN
x1
x2
x4
x8
x16
x32
x64
x128
mapped to the correct output range. Note U/B must be
set before a conversion is performed; it will not affect
any data already held in the output register.
Selecting bipolar mode does not imply that any input
may be taken below AGND. It simply changes the gain
and offset of the part. All inputs must remain within their
specified operating voltage range.
Offset-Correction DACs
Bits D3–D0 control the offset-correction DAC. The DAC
range depends on the PGA gain setting and is
expressed as a percentage of the available full-scale
input range (Table 7).
D3 is a sign bit, and D2–D0 represent the DAC magni-
tude. Note that when a DAC value of 0000 is pro-
grammed (the default), the DAC is disconnected from
the modulator inputs. This prevents the DAC from
degrading noise performance when offset correction is
not required.
Transfer-Function Register Mapping
Tables 8, 9, and 10 show the channel-control register
mapping in the various operating modes.
Table 7. DAC Code vs. DAC Value
D3 D2 D1 D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BIPOLAR
DAC VALUE
(% of FSR)
UNIPOLAR
DAC VALUE
(% of FSR)
DAC not connected
+8.3
+16.7
+16.7
+33.3
+25
+50
+33.3
+66.7
+41.6
+83.3
+50
+100
+58.3
+116.7
DAC not connected
-8.3
-16.7
-16.7
-33.3
-25
-50
-33.3
-66.7
-41.6
-83.3
-50
-100
-58.3
-116.7
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