MAX1248 Datasheet, PDF (7/24 Pages) Maxim Integrated Products – 2x4-Channel, Simultaneous-Sampling 14-Bit DAS

+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1
V_DD
Positive Supply Voltage
2–5
CH0–CH3 Sampling Analog Inputs
6
COM
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1249 down; otherwise, the
7
SHDN
devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compen-
sation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
8
VREF
internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to V_DD.
9
REFADJ
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V_DD.
10
AGND
Analog Ground
11
DGND
Digital Ground
12
DOUT
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the
13
SSTRB
A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
14
DIN
Serial Data Input. Data is clocked in at SCLK’s rising edge.
15
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
16
SCLK
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
V_DD
DOUT
6k
DOUT
6k
DGND
C_LOAD
50pF
C_LOAD
50pF
DGND
a) High-Z to V_OH and V_OL to V_OH
b) High-Z to V_OL and V_OH to V_OL
Figure 1. Load Circuits for Enable Time
V_DD
DOUT
6k
DGND
DOUT
C_LOAD
50pF
6k
C_LOAD
50pF
DGND
a) V_OH to High-Z
b) V_OL to High-Z
Figure 2. Load Circuits for Disable Time
_______________________________________________________________________________________ 7