MAX1248 Datasheet, PDF (20/24 Pages) Maxim Integrated Products – 2x4-Channel, Simultaneous-Sampling 14-Bit DAS

+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
+3V +3V
0.1µF
ANALOG
INPUTS
+2.5V
0.1µF
1 V_DD
SCLK ¹⁶
2 CH0
CS 15
3
CH1
MAX1248
MAX1249
DIN
14
4 CH2
SSTRB 13
5 CH3
DOUT 12
6 COM
DGND 11
7 SHDN
AGND 10
8 VREF
REFADJ 9
1µF
SCK
PCS0
MC683XX
MOSI
MISO
CLOCK CONNECTIONS NOT SHOWN
(GND)
Figure 19. MAX1248/MAX1249 QSPI Connections External Reference
TMS320LC3x Interface
Figure 20 shows an application circuit to interface the
MAX1248/MAX1249 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 21.
Use the following steps to initiate a conversion in the
MAX1248/MAX1249 and to read the results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
tied together with the MAX1248/MAX1249’s SCLK
input.
2) The MAX1248/MAX1249’s CS pin is driven low by
the TMS320’s XF_ I/O port, to enable data to be
clocked into the MAX1248/MAX1249’s DIN.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1248/MAX1249 to initiate a conversion and
place the device into external clock mode. Refer to
Table 1 to select the proper XXXXX bit values for
your specific application.
4) The MAX1248/MAX1249’s SSTRB output is moni-
tored via the TMS320’s FSR input. A falling edge on
the SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX1248/MAX1249.
XF
CLKX
TMS320LC3x
CLKR
DX
DR
FSR
CS
SCLK
MAX1249
DIN
DOUT
SSTRB
Figure 20. MAX1248/MAX1249-to-TMS320 Serial Interface
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 10 + 2-bit conversion result followed by
four trailing bits, which should be ignored.
6) Pull CS high to disable the MAX1248/MAX1249 until
the next conversion is initiated.
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