MAX1248 Datasheet, PDF (11/24 Pages) Maxim Integrated Products – 2x4-Channel, Simultaneous-Sampling 14-Bit DAS

+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
CS
SCLK
1
t_ACQ
4
8
DIN
SSTRB
DOUT
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
START
RB1
A/D STATE
ACQUISITION
IDLE
1.5µs
(f_CLK = 2MHz)
12
16
20
24
RB2
RB3
B9
MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
FILLED WITH
S0 _ZEROS
CONVERSION
IDLE
Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f_SCLK ≤ 2MHz)
CS
SCLK
DIN
DOUT
t_CSS
t_CSH
t_DS
t_DH
t_DV
•••
t_CH
t_CL
•••
•••
•••
t_CSH
t_DO
t_TR
Figure 6. Detailed Serial-Interface Timing
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 7 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
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