MAX1205 Datasheet, PDF (7/12 Pages) Maxim Integrated Products – +5v sINGLE-sUPPLY, 1mSPS, 14-bIT sELF-cALIBRATING adc

+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
Pin Description (continued)
PIN
25
26
27, 30
31
32
NAME
TEST2
TEST1
DV_DD
CLK
DAV
33
OE
34
35
36
37
38
39
40
41, 42
43
TEST0
CM
RFPF
RFPS
RFNF
RFNS
INP
N.C.
INN
44 END_CAL
FUNCTION
Test Pin 2. Leave unconnected.
Test Pin 1. Leave unconnected.
Digital Power Supply, +3V to +5.25V
Input Clock. Receives power from AV_DD to reduce jitter.
Data Valid Clock Output. This clock can be used to transfer the data to a memory or any other
data-acquisition system.
Output Enable Input.
OE = 0: D0-D13 and DOR are high impedance.
OE = 1: All bits are active.
Test Pin 0. Leave unconnected.
Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages.
Positive Reference Voltage. Force input.
Positive Reference Voltage. Sense input.
Negative Reference Voltage. Force input.
Negative Reference Voltage. Sense input.
Positive Input Voltage
Not Connected. No internal connection.
Negative Input Voltage
Digital Output for End of Calibration.
END_CAL = 0: Calibration in progress.
END_CAL = 1: Normal conversion mode.
_______________Detailed Description
Converter Operation
The MAX1205 is a 14-bit, monolithic, analog-to-digital
converter (ADC) capable of conversion rates up to
1Msps. It uses a multistage, fully differential pipelined
architecture with digital error correction and self-cali-
bration to provide typically greater than 91dB spurious-
free dynamic range at a 1Msps sampling rate. Its
signal-to-noise ratio, harmonic distortion, and intermod-
ulation products are also consistent with 14-bit accura-
cy up to the Nyquist frequency. This makes the device
suitable for applications such as imaging, scanners,
data acquisition, and digital communications.
Figure 1 shows the simplified, internal structure of the
ADC. A switched-capacitor pipelined architecture is
used to digitize the signal at a high throughput rate.
The first four stages of the pipeline use a low-resolution
quantizer to approximate the input signal. The multiply-
ing digital-to-analog converter (MDAC) stage is used to
subtract the quantized analog signal from the input.
The residue is then amplified with a fixed gain and
passed on to the next stage. The accuracy of the con-
verter is improved by a digital calibration algorithm
which corrects for mismatches between the capacitors
in the switched capacitor MDAC. Note that the pipeline
introduces latency of four sampling periods between
the input being sampled and the output appearing at
D13–D0.
While the device can handle both single-ended and dif-
ferential inputs (see Requirements for Reference and
Analog Signal Inputs), the latter mode of operation will
guarantee best THD and SFDR performance. The dif-
ferential input provides the following advantages com-
pared to a single-ended operation:
• Twice as much signal input span
• Common-mode noise immunity
• Virtual elimination of the even-order harmonics
• Less stringent requirements on the input signal
processing amplifiers
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