MAX1205 Datasheet, PDF (10/12 Pages) Maxim Integrated Products – +5v sINGLE-sUPPLY, 1mSPS, 14-bIT sELF-cALIBRATING adc

+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
divide-by-two circuit, which relaxes this requirement.
The clock generator should be chosen commensurate
with the frequency range, amplitude, and slew rate of
the signal source. If the slew rate of the input signal is
small, the jitter requirement on the clock is relaxed.
However, if the slew rate is high, the clock jitter needs
to be kept at a minimum. For a full-scale amplitude
input sine wave, the maximum possible signal-to-noise
ratio (SNR) due completely to clock jitter is given by:
SNR_MAX
=
1
2πf_INσ _JITTER
For example, if f_IN is 0.5MHz and σ_JITTER is 20ps RMS,
then the SNR limit due to jitter is about 84dB. Generating
such a clock source requires a low-noise comparator
and a low-phase-noise signal generator. The clock cir-
cuit shown in Figure 6 is a possible solution.
Calibration Procedure
Since the MAX1205 is based on a pipelined architec-
ture, low-resolution quantizers (“coarse ADCs”) are
used to approximate the input signal. MDACs of the
same resolution are then used to reconstruct the input
signal, which is subtracted from the input and the
residue amplified by the SC gain stage. This residue is
then passed on to the next stage.
The accuracy of the MAX1205 is limited by the preci-
sion of the MDAC, which is strongly dependent on the
matching of the capacitors used. The mismatch
between the capacitors is determined and stored in an
on-chip memory, which is later used during the conver-
sion of the input signal.
During the calibration procedure, the clock must be
running continuously. ST_CAL (start of calibration) is
V+
0.1µF
CLK_IN
1k
V+
5k _MAX961
0.1µF
CLK
initiated by a positive pulse with a minimum width of
four clock cycles, but no longer than about 17,400
clock cycles (Figure 8).
The ST_CAL input may be asynchronous with the clock,
since it is retimed internally. With ST_CAL activated,
END_CAL goes low one or two clock cycles later and
remains low until the calibration is complete. During this
period, the reference voltages must be stable to less
than 0.01%; otherwise the calibration will be invalid.
During calibration, the analog inputs INP and INN are
not used; however, better performance is achieved if
these inputs are static. Once END_CAL goes high (indi-
cating that the calibration procedure is complete), the
ADC is ready for conversion.
Once calibrated, the MAX1205 is insensitive to small
changes (<5%) in power-supply voltage or tempera-
ture. Following calibration, if the temperature changes
more than ±20°C, the device should be recalibrated to
maintain optimum performance.
N
AIN
CLK
SAMPLE
CLOCK
t_S
DAV
D0–D13
N+1
N+5
N+2 _N+3
N+4
t_CH t_CL
t_OD
N-3 N-2
N-1
N N+1
Figure 7. Main Timing Diagram
CLK
ST_CAL
END_CAL
min 4 t_CLK
~17,400 CLK Cycles
Figure 8. Timing for Start and End of Calibration
0.1µF
1k
OE
t_AC
t_REL
D0–D13
DOR
Z
Z
Figure 6. Clock Generation Circuit Using a Low-Noise
Comparator
Figure 9. Timing for Bus Access and Bus Relinquish—
Controlled by Output Enable (OE)
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