MAX1112 Datasheet, PDF (7/20 Pages) Maxim Integrated Products – 5V, Low-Power, Multi-Channel, Serial 8-Bit ADCs Internal 4.096V Reference

+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
PIN
MAX1112
1–4
5–8
MAX1113
1–4
—
9
5
10
6
11
7
12
8
13
9
14
10
15
11
16
12
17
13
18
14
19
15
20
16
NAME
CH0–CH3
CH4–CH7
COM
SHDN
REFIN
REFOUT
AGND
DGND
DOUT
SSTRB
DIN
CS
SCLK
V_DD
Pin Description
FUNCTION
Sampling Analog Inputs
Sampling Analog Inputs
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5 LSB.
Three-Level Shutdown Input. Normally high impedance. Pulling SHDN low shuts the
MAX1112/MAX1113 down to 10µA (max) supply current; otherwise, the devices are
fully operational. Pulling SHDN high shuts down the internal reference.
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND.
Analog Ground
Digital Ground
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1112/
MAX1113 begin the A/D conversion and goes high when the conversion is complete.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
high, DOUT is high impedance.
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%).
Positive Supply Voltage, 4.5V to 5.5V. Bypass to AGND with 0.1µF and 1µF capacitor
as close as possible to the device. Place the 0.1µF capacitor closer to V_P-P.
+5V
DOUT
3kΩ
DOUT
3kΩ
C_LOAD
C_LOAD
DGND
DGND
a) High-Z to V_OH and V_OL to V_OH
b) High-Z to V_OL and V_OH to V_OL
+5V
DOUT
3kΩ
DOUT
3kΩ
DGND
C_LOAD
C_LOAD
DGND
a) V_OH to High-Z
b) V_OL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
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