MAX1112 Datasheet, PDF (5/20 Pages) Maxim Integrated Products – 5V, Low-Power, Multi-Channel, Serial 8-Bit ADCs Internal 4.096V Reference

+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
TIMING CHARACTERISTICS (Figures 8 and 9)
(V_DD = 4.5V to 5.5V, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Track/Hold Acquisition Time
t_ACQ
1
DIN to SCLK Setup
t_DS
100
DIN to SCLK Hold
t_DH
0
SCLK Fall to Output Data Valid
t_DO
Figure 1, C_LOAD = 100pF
20
CS Fall to Output Enable
t_DV
Figure 1, C_LOAD = 100pF
CS Rise to Output Disable
t_TR
Figure 2, C_LOAD = 100pF
CS to SCLK Rise Setup
t_CSS
100
CS to SCLK Rise Hold
t_CSH
0
SCLK Pulse Width High
t_CH
200
SCLK Pulse Width Low
t_CL
200
SCLK Fall to SSTRB
t_SSTRB C_LOAD = 100pF
CS Fall to SSTRB Output Enable
(Note 5)
t_SDV
Figure 1, external clock mode only,
C_LOAD = 100pF
CS Rise to SSTRB Output
Disable (Note 5)
t_STR
Figure 2, external clock mode only,
C_LOAD = 100pF
µs
ns
ns
200
ns
240
ns
240
ns
ns
ns
ns
ns
240
ns
240
ns
240
ns
SSTRB Rise to SCLK Rise
(Note 5)
t_SCK Figure 11, internal clock mode only
0
ns
Wakeup Time
t_WAKE
External reference
Internal reference (Note 10)
20
µs
24
ms
Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2: V_REFIN = 4.096V, offset nulled.
Note 3: On-channel grounded; sine wave applied to all off-channels.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Common-mode range for the analog inputs is from AGND to V_DD.
Note 7: External load should not change during the conversion for specified accuracy.
Note 8: External reference at 4.096V, full-scale input, 500kHz external clock.
Note 9: Measured as | V_FS (4.5V) - V_FS (5.5V) |.
Note 10: 1µF at REFOUT; internal reference settling to 0.5 LSB.
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