DS1743 Datasheet, PDF (7/16 Pages) Dallas Semiconductor – Y2KC Nonvolatile Timekeeping RAM

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITING DATA TO RAM OR CLOCK
The DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout the
cycle. CE or WE must return inactive for a minimum of t_WR prior to the initiation of another read or write
cycle. Data in must be valid t_DS prior to the end of write and remain valid for t_DH afterward. In a typical
application, the OE signal will be high during a write cycle. However, OE can be active provided that care
is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus
can become active with read data defined by the address inputs. A low transition on WE will then disable
the outputs t_WEZ after WE goes active.
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when V_CC is below the power-fail point, V_PF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time (PowerCap only) the power-
fail reset-output signal (RST) is driven active and remains active until V_CC returns to nominal levels. When
V_CC falls below the battery switch point V_SO (battery supply level), device power is switched from the V_CC
in to the backup battery. RTC operation and SRAM data are maintained from the battery until V_CC is
returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when V_CC is greater than V_PF.
When V_CC falls below the power-fail point, V_PF, access to the device is inhibited. At this time the power-
fail reset-output signal (RST) is driven active and remains active until V_CC returns to nominal levels. If V_PF
is less than V_SO, the device power is switched from V_CC to the backup supply (V_BAT) when V_CC drops
below V_PF. If V_PF is greater than V_SO, the device power is switched from V_CC to the backup supply (V_BAT)
when V_CC drops below V_SO. RTC operation and SRAM data are maintained from the battery until V_CC is
returned to nominal levels. The RST (PowerCap only) signal is an open-drain output and requires a pullup
resistor. Except for RST, all control, data, and address signals must be powered down when V_CC is
powered down.
BATTERY LONGEVITY
The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the V_CC supply is not present. The capability of this internal power supply is
sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running in
the absence of V_CC power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When V_CC is first applied at a level greater than
V_PF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1743 will be longer than 10 years since no lithium battery energy is consumed when V_CC is present.
BATTERY MONITOR
The DS1743 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writeable and
should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and
both the contents of the RTC and RAM are questionable.
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