DS1743 Datasheet, PDF (3/16 Pages) Dallas Semiconductor – Y2KC Nonvolatile Timekeeping RAM

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
VOLTAGE
(V)
TOP MARK**
DS1743-85
DS1743-100
DS1743-100 IND
DS1743P-85
DS1743P-100
DS1743P-100IND
DS1743W-120
DS1743W-120 IND
DS1743W-150
DS1743W-150 IND
DS1743WP-120
DS1743WP-120 IND
DS1743-85+
DS1743-100+
DS1743-100 IND+
DS1743P-85+
DS1743P-100+
DS1743P-100IND+
DS1743W-120+
DS1743W-120 IND+
DS1743W-150+
DS1743W-150 IND+
DS1743WP-120+
DS1743WP-120 IND+
DS9034PCX
DS9034I-PCX
DS9034PCX+
DS9034I-PCX+
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
28 EDIP Module
28 EDIP Module
28 EDIP Module
34 PowerCap*
34 PowerCap*
34 PowerCap*
28 EDIP Module
28 EDIP Module
28 EDIP Module
28 EDIP Module
34 PowerCap*
34 PowerCap*
28 EDIP Module
28 EDIP Module
28 EDIP Module
34 PowerCap*
34 PowerCap*
34 PowerCap*
28 EDIP Module
28 EDIP Module
28 EDIP Module
28 EDIP Module
34 PowerCap*
34 PowerCap*
PowerCap
PowerCap IND
PowerCap
PowerCap IND
5
DS1743-85
5
DS1743-100
5
DS1743-100-IND
5
DS1743P-85
5
DS1743P-100
5
DS1743P-100 IND
3.3
DS1743W-120
3.3
DS1743W-120 IND
3.3
DS1743W-150
3.3
DS1743W-150 IND
3.3
DS1743WP-120
3.3
DS1743WP-120 IND
5
DS1743-85
5
DS1743-100
5
DS1743-100-IND
5
DS1743P-85
5
DS1743P-100
5
DS1743P-100 IND
3.3
DS1743W-120
3.3
DS1743W-120 IND
3.3
DS1743W-150
3.3
DS1743W-150 IND
3.3
DS1743WP-120
3.3
DS1743WP-120 IND
—
DS9034PC
—
DS9034PCI
—
DS9034PC
—
DS9034PCI
+Denotes a lead-free package.
*DS9034PCX required (must be ordered separately).
**A ‘+’ indicates lead-free. The top mark will include a ‘+’ symbol on lead-free devices.
DESCRIPTION
The DS1743 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8
nonvolatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide
interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM
locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in
24-hour binary-coded decimal (BCD) format. Corrections for the day of the month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur
during clock update cycles. The double-buffered system also prevents time loss as the timekeeping
countdown continues unabated by access to time register data. The DS1743 also contains its own power-
fail circuitry, which deselects the device when the V_CC supply is in an out-of-tolerance condition. When
V_CC is above V_PF, the device is fully accessible. When V_CC is below V_PF, the internal CE signal is forced
high, preventing any access. When V_CC rises above V_PF, access remains inhibited for T_REC, allowing time
for the system to stabilize. These features prevent loss of data from unpredictable system operation brought
on by low V_CC as errant access and update cycles are avoided.
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