MAX16063 Datasheet, PDF (6/13 Pages) Maxim Integrated Products – 1% Accurate, Low-Voltage, Quad Window Voltage Detector

1% Accurate, Low-Voltage,
Quad Window Voltage Detector
PIN
1
2
3
4
5
6
7, 24
8
9
10
11
12
13
14
Pin Description
NAME
UVIN3
OVIN3
UVIN4
OVIN4
N.C.
GND
V_CC
UVOUT3
OVOUT3
UVOUT4
OVOUT4
MR
SRT
MARGIN
FUNCTION
Undervoltage Threshold Input 3. When the voltage on UVIN3 falls below its threshold, UVOUT3 asserts low.
Overvoltage Threshold Input 3. When the voltage on OVIN3 rises above its threshold, OVOUT3 asserts low.
Undervoltage Threshold Input 4. When the voltage on UVIN4 falls below its threshold, UVOUT4 asserts low.
Overvoltage Threshold Input 4. When the voltage on OVIN4 rises above its threshold, OVOUT4 asserts low.
No Connection. Not internally connected.
Ground
Unmonitored Power to the Device
Active-Low Undervoltage Output 3. When the voltage at UVIN3 falls below its threshold, UVOUT3 asserts
low and stays asserted until the voltage at UVIN3 exceeds its threshold. The open-drain output has a 30µA
internal pullup to V_CC.
Active-Low Overvoltage Output 3. When the voltage at OVIN3 rises above its threshold, OVOUT3 asserts
low and stays asserted until the voltage at OVIN3 falls below its threshold. The open-drain output has a
30µA internal pullup to V_CC.
Active-Low Undervoltage Output 4. When the voltage at UVIN4 falls below its threshold, UVOUT4 asserts
low and stays asserted until the voltage at UVIN4 exceeds its threshold. The open-drain output has a 30µA
internal pullup to V_CC.
Active-Low Overvoltage Output 4. When the voltage at OVIN4 rises above its threshold, OVOUT4 asserts
low and stays asserted until the voltage at OVIN4 falls below its threshold. The open-drain output has a
30µA internal pullup to V_CC.
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout
period after MR is deasserted. MR is pulled up to V_CC through a 20kΩ resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset
timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 10⁶ (Ω) x C_SRT (F). For the internal
timeout period of 140ms (min), connect SRT to V_CC.
Active-Low Margin Enable Input. Pull MARGIN low to deassert all outputs (go into high state) regardless of
the voltage at any monitored input.
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