MAX16063 Datasheet, PDF (11/13 Pages) Maxim Integrated Products – 1% Accurate, Low-Voltage, Quad Window Voltage Detector

1% Accurate, Low-Voltage,
Quad Window Voltage Detector
RESET Output
RESET asserts low when the voltage on any of the
UVIN_ inputs falls below its respective threshold, the
voltage on any of the OVIN_ inputs goes above its
respective threshold, or MR is asserted. RESET
remains asserted for the reset timeout period after all
monitored UVIN_ inputs exceed their respective thresh-
olds, all OVIN_ inputs fall below their respective thresh-
olds, and MR is deasserted (see Figure 6). This
open-drain output has a 30µA internal pullup.
Reset Timeout Capacitor
The reset timeout period can be adjusted to accommo-
date a variety of microprocessor (µP) applications.
Adjust the reset timeout period (t_RP) by connecting a
capacitor (C_SRT) between SRT and GND. Calculate the
reset timeout capacitor as follows:
C_SRT
(F)
=
⎛
t_RP (s)
V_{TH_ SRT}
⎞
⎝⎜ I_SRT ⎠⎟
Connect SRT to V_CC for a factory-programmed reset
timeout of 140ms (min).
Manual Reset Input (MR)
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low, and during the reset timeout period (140ms min)
after MR returns high. The MR input has an internal
20kΩ pullup resistor to V_CC, so it can be left open if it is
not used. MR can be driven with TTL or CMOS-logic
levels, or with open-drain/collector outputs. Connect a
normally open momentary switch from MR to GND to
create a manual reset function; external debounce cir-
cuitry is not required. If MR is driven from long cables
or if the device is used in a noisy environment, connect-
ing a 0.1µF capacitor from MR to GND provides addi-
tional noise immunity.
V_CC = 3.3V
5V
100kΩ
V_CC
V_CC
UVOUT_
RESET
MAX16063
GND
GND
Figure 5. Interfacing to a Different Logic Supply Voltage
UVIN_
VTH_
RESET
UVOUT_
10%
tRD
10%
tD
VTH_ + VTH_HYS
90%
tRP
90%
tD
VTH_
OVIN_
OVOUT_
10%
tD
Figure 6. Output Timing Diagram
VTH_ - VTH_HYS
90%
tD
______________________________________________________________________________________ 11